How can I drive complex input in DUT? Can I generate that complex input using reference model that generated input drive in DUT using driver?
Is there any another possibility?
Please give me best suggestions
In reply to rahul pawar:
What do you mean with ‘complex input’. A DUT has pads/pins which are relating to wires (not Verilog wire). There is nothing complex.
In reply to chr_sue:
hello sir,
I am trying to verify Ethernet receiver it’s input is 1bit mdi. that mdi is represent complete encoded Ethernet frame.
So how can I generate that mdi and drive to the DUT ?
Can you please suggest what should be my strategy to drive complex input?
In reply to rahul pawar:
7byte(preamble),1byte(SFD),6byte(destinations address),6byte(source address),2byte(payload length),46to1500byte(payload),4byte(CRC)
my input is derivative to this frame (i mean that 1bit mdi is complete encoded to this frame)
so I have to drive lots of 1bit-mdi for 1-package. and it’s to complex and difficult to debugging.
sir please give me suggestions for it. how can i drive complex input to DUT?
can I use uvm_subscriber for generate that complex input?
In reply to rahul pawar:
You should watch the videos here
https://verificationacademy.com/courses/uvm-basics
to understand how you can go ahead