How can i connect two sequencers to regmodel

UVM
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1

Hi,
im having a reg_model in my env.
And i want to connect it to two sequencers, so i could write function:
reg_model.register.write
but this syntax is relevant for one sequencer.
what can i do if i want to use two sequencers and how can i do it?

Thanks for any help.

2

The register model assumes that you will access all registers contained within the register map via one interface, which is why it allows only one sequencer to be registered.

Is there a specific reason that you want to access the same registers via two separate interfaces? If they are separate register sets, then I would recommend having two individual register models and connect each one to the appropriate sequencer.

3

In reply to cgales:

The reason that i want to do it is im having 2 active agents which each one of them can write to those registers.
if i’ll do two register models each one of them will hold different database.
I need that if agentA write to register reg1 and agentb will read from this register then it will holds the same data that agentA has write.

4

In reply to Adir Levi:

So these two agents are on separate interfaces? Are the register maps identical with respect to each interface (i.e. the same address is used for each interface)?

While the register model does provide the self-checking capabilities, using two models will preclude some of those features. In this case, I would turn off that feature and use the models simply for the read/write functionality.

How will your test determine which interface to use for read/write access? What if a test focuses on one interface only? If so, you can use the self checking capabilities and simply ignore the second interface.

5

cgales,
I have a similar situation as Adir
So these two agents are on separate interfaces? Are the register maps identical with respect to each interface (i.e. the same address is used for each interface)?
→ Yes.

While the register model does provide the self-checking capabilities, using two models will preclude some of those features. In this case, I would turn off that feature and use the models simply for the read/write functionality.
→ if I use two models hoe do I sync my mirror values.

How will your test determine which interface to use for read/write access? What if a test focuses on one interface only? If so, you can use the self checking capabilities and simply ignore the second interface.
→ thru config test can decide which interface to use. no issue here.

BTW only the latest/last of .set_sequencer in env for each of the interfaces is effective.is there a way to set two sequencers.
Pls clarify

6

In reply to sankardr:

There are two solutions for this problem. Though I haven’t tried any.

  1. Have two separate Register Maps for each interface. Also, you need to connect two Analysis Port, each Interface Monitor, with Predictor’s uvm_analysis_imp#() bus_in.
my_monitor1.mon_ap.connect(my_reg_predictor.bus_in);
my_monitor2.mon_ap.connect(my_reg_predictor.bus_in);
  1. Use only one Register Map, but connect sequencer to this map dynamically before starting the sequence. Adapter can be common based on Sequence Item type on each Interface.
// Testcase

// Set Interface-1 Sequencer to given Register Map
env_cfg.my_reg_block.reg_map.set_sequencer(.sequencer(my_agent1.my_seqr), .adapter( my_env.my_reg_adapter));

//Writing with Interface-1
env.my_reg_block.reg_map.MY_REGISTER.write(status, value, UVM_FRONTDOOR);


// Set Interface-2 Sequencer to given Register Map
env_cfg.my_reg_block.reg_map.set_sequencer(.sequencer(my_agent2.my_seqr), .adapter( my_env.my_reg_adapter));

//Writing with Interface-2
env.my_reg_block.reg_map.MY_REGISTER.write(status, value, UVM_FRONTDOOR);