How to call a vhdl procedure inside a System-Verilog UVM Class?

UVM
1

Hello,

I was trying to access a vhdl-procedure written in a pkg file inside UVM CLASS written in System Verilog.

I have tried several means but it does not work.

Looking forward to some solutions.

Best Regards,
Pratyaksha

2

At this time, no, you cannot directly call a VHDL procedure from a task/function from in SystemVerilog, or the reverse.

What you can do is create a set of handshaking signals - one that triggers the start of the task, and another that triggers the end of the task. These signals can be passed through ports at the mixed language boundary, or you can use $signal_spy if your simulator is Questa. The arguments to your tasks/functions will also need to be passed as ports or use $signal_spy.

3

In reply to dave_59:

At this time, no, you cannot directly call a VHDL procedure from a task/function from in SystemVerilog, or the reverse.

And today?

4

In reply to VeriEngineer:

No Change. It is extremely difficult to get different standards bodies to work together to make this happen without strong user demand.

5

In reply to dave_59:

Dave, Is it possible to provide an example for this. I am trying to use the VHDL model developed by designers and due to project schedule, I would like to use the existing model and need to use the VHDL write and read procedure for writing and reading to/from registers. The one solution you mentioned above seems to fit what I wanted to do, but if you give an example of how it can done would really help.

Thanks
Ram