in the interface_connect.sv i want to assign the signals above inside a genvar loop:
string init_done_path,init_bsy_path;
generate
for (genvar x=0; x<NUM_X; x++) begin
for (genvar y=0; y<NUM_Y; y++) begin
initial begin
init_done_path = $sformatf("`DUT_TOP.dpm.dpu_%0d_%0d.init",x,y);
init_bsy_path = $sformatf("`DUT_TOP.dpm.dpu_%0d_%0d.init_bsy",x,y);
assign `HADAS_INT_IF.dpbm_init_done[HADAS_NUM_DPUS_X*dpu_x+dpu_y] = init_done_path;
assign `HADAS_INT_IF.mbr_init_bsy[HADAS_NUM_DPUS_X*dpu_x+dpu_y] = init_bsy_path;
end
end
end
endgenerate
This code if, of course, not working. The RHS of the assign is a string, and not a path, and I also hit errors like Invalid use of pattern.
and in the interface_connect.sv (this is where I want to asign vif.signal from concatenation of gen vars):
assign `DUT_INT_IF.rmu_rst_n = `DUT_TOP.glc3.rmu_top_i.rst_n; // this is straight forward :-)
generate
for (genvar x=0; x<NUM_DPUS_X; x++) begin
for (genvar y=0; y<NUM_DPUS_Y; y++) begin
initial begin
init_done_path = $sformatf("`DUT_TOP.dpm.dpu_%0d_%0d.init",dpu_x,dpu_y);
init_bsy_path = $sformatf("`DUT_TOP.dpm.dpu_%0d_%0d.init_bsy",dpu_x,dpu_y);
assign `HADAS_INT_IF.dpbm_init_done[HADAS_NUM_DPUS_X*dpu_x+dpu_y] = init_done_path;
assign `HADAS_INT_IF.mbr_init_bsy[HADAS_NUM_DPUS_X*dpu_x+dpu_y] = init_bsy_path;
end
end
end
endgenerate
In reply to tsafrirw:
Please describe your problem
. Do you want to connect the vector slices from the interface variable to different signals in your DUT or do you wan to connect the vector to the same size vector?
What is the error message you are facing?
I want to connect a member of the interface (interface variable) to a signal in the DUT.
I am asking for help in connecting the interface variable in a case where the signal depends on the genvar:
generate
for (genvar x=0; x<NUM_X; x++) begin
for (genvar y=0; y<NUM_Y; y++) begin
initial begin
init_done_path = $sformatf(“DUT_TOP.dpm.dpu_%0d_%0d.init",x,y); init_bsy_path = $sformatf("DUT_TOP.dpm.dpu_%0d_%0d.init_bsy”,x,y);
**assign** `HADAS_INT_IF.dpbm_init_done[HADAS_NUM_DPUS_X*dpu_x+dpu_y] = init_done_path;
**assign** `HADAS_INT_IF.mbr_init_bsy[HADAS_NUM_DPUS_X*dpu_x+dpu_y] = init_bsy_path;
end
end
end
endgenerate
in the assign above, the DUT signal’s path depends on the genvar. It is not working because the LHS of the assign is of type logic and the RHS is of type string. Basically, I would like your advice on how to allow such assignment.
Please use code tags making your code easier to read. I have added them for you.
You cannot convert strings to identifier names in SystemVerilog. What you can do is make sure the path names are created using a generate or array of instances.
for (genvar x=0; x<NUM_DPUS_X; x++) begin
for (genvar y=0; y<NUM_DPUS_Y; y++) begin
initial begin
assign `HADAS_INT_IF.dpbm_init_done[HADAS_NUM_DPUS_X*x+y] = `DUT_TOP.dpm.dpu[x][y].init;
assign `HADAS_INT_IF.mbr_init_bsy[HADAS_NUM_DPUS_X*x+y] = `DUT_TOP.dpm.dpu[x][y].init_bsy;
end
end