How to access a subcomponent register block

UVM
1

Hello,
How to build a subcomponent register block model from the top level env ? And also how to acess it in the testcases ?
Please point me to an example if possible?

I tried to look in the UVM cookbook but couldn’t understand to do it if we have subcomponent register blocks.

This is the statement from UVM cookbook “A cluster, or sub-system, level register model will have a register block which will contain other register model blocks for each of the sub-components in the cluster, and register maps for each of the bus interfaces. At this level, a register map can specify an offset address for a sub-block and the accesses to the registers within that sub-block will be adjusted to generate the right address within the cluster level map.”

I have the register model file automatically generated , so that is not an issue.

Could someone please point to examples to build it in the top level env and how to access it in the testcases .

Thankyou

2

In reply to nijohn:

There is an example in the cookbook of a sub-system register block. It’s under Registers/ModelStructure, heading Register Blocks. Look for “package pss_reg_pkg”.

At the block level, the register block will contain registers and/or memory. At sub-system level, you instantiate the block level register block(s). Then you use a uvm_reg_map to apply a memory map to these component-level register blocks.

Could someone please point to examples to build it in the top level env and how to access it in the testcases .

You build the register block in the test base, not the environment. This allows your sequences to get access to it; the test can assign a pointer.