class A_agent extends uvm_agent;
`uvm_component_utils(A_agent)
function new(string name = “”,uvm_component parent);
super.new(name,parent);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
h_driver.seq_item_port.connect(h_seqr.seq_item_export);
endfunction
endclass
error:** Error: (vsim-7065) Illegal assignment to class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_port_base #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sqr_if_base #(class work.pkg::seq_item, class work.pkg::seq_item)) from class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_seq_item_pull_imp #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item, class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item, class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequencer #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item, class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item))
** Error: (vsim-8754) Actual input arg. of type ‘class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_seq_item_pull_imp #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item, class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item, class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequencer #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item, class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sequence_item))’ for formal ‘provider’ of ‘connect’ is not compatible with the formal’s type ‘class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_port_base #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_sqr_if_base #(class work.pkg::seq_item, class work.pkg::seq_item))’.
In reply to ABD_91:
//----------driver----------------//
class driver extends uvm_driver #(seq_item);
`uvm_component_utils(driver)
function new(string name = “”,uvm_component parent);
super.new(name,parent);
endfunction
virtual example h_vintf;
task run_phase(uvm_phase phase);
super.run_phase(phase);
forever begin
@(h_vintf.cb_driver) begin
seq_item_port.get_next_item(req);
h_vintf.cb_driver.rst <= req.rst;
h_vintf.cb_driver.b<= req.b;
h_vintf.cb_driver.c <= req.c;
seq_item_port.item_done();
end
end
endtask
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if(!uvm_config_db#(virtual example)::get(this,"*","key",h_vintf)) `uvm_fatal("MSG","CONFIG_DB");
endfunction
endclass
//-----------sequencer--------------//
class sequencer extends uvm_sequencer;
`uvm_component_utils(sequencer)
function new(string name = “” ,uvm_component parent);
super.new(name,parent);
endfunction
endclass