Hi , i developed uvm tb for spi master core, when i am running tb with single test case , it was went up to master monitor and it is looping there it self due to forever in monitor run task,how to overcome this?

UVM
1

class wb_monitor extends uvm_monitor;

//factory registration

`uvm_component_utils(wb_monitor)

//constructor

function new (string name=“wb_monitor”,uvm_component parent);
super.new(name,parent);
endfunction

virtual wb_intf vif; //virtual interface handle
wb_seq_item txn;
uvm_analysis_port #(wb_seq_item) wb_mon_analysis; //analysis port

//build phase

virtual function void build_phase (uvm_phase phase);
super.build_phase (phase);
txn= wb_seq_item::type_id::create(“txn”); //Declare a sequence item handle and create object
wb_mon_analysis = new(“wb_mon_analysis”,this);
if (! uvm_config_db #(virtual wb_intf) :: get (this, “”, “vif”, vif))
begin
`uvm_fatal (get_type_name (), “Didn’t get handle to virtual interface if_name”)
end
endfunction :build_phase

//RUN PHASE
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
`uvm_info( get_type_name(), “waiting for wishbone seq item sample”, UVM_MEDIUM)

forever begin

@(posedge vif.wb_clk_i);
begin

txn.wb_sel_i=vif.`W_MON.wb_sel_i;
…
…

wb_mon_analysis.write(txn);
end
end
endtask

endclass

2

In reply to kathula venkatesh:

It behaves as you have coded the monitor. And the monitor needs a forever loop. But you do not show the details how you are putting the transaction together.
What is your problem? Does the simulation not come to its end?

3

In reply to chr_sue:

yes, simulation is not come to its end, forever inside monitor is continuously executing.

4

In reply to kathula venkatesh:

This is an indication something in your monitor is going wrong or it happens somewhere else. Could you please show how you assemble the transaction un the monitor
BTW, seq_items will not be constructed in the build_phase. . They do not belong to the topology of your testbench.

5

In reply to chr_sue:

this my sequence
class sl_seq1 extends slave_sequence;

`uvm_object_utils(sl_seq1)

function new (string name=“sl_seq1”);
super.new(name);
endfunction

spi_seq_item seq;

virtual task body();

seq=spi_seq_item::type_id::create("seq"); //create the seq item

start_item(seq);

	assert (seq.randomize() with {spi_miso inside {[0:1000]};})
	`uvm_info("seq1","seq1 was randomised in between 0 to 1000",UVM_MEDIUM)
finish_item(seq);

endtask :body

endclass :sl_seq1

this is my monitor code

`define MON spi_mon.spi_mon_cb
class spi_monitor extends uvm_monitor;

`uvm_component_utils(spi_monitor)
virtual wb_intf vif;
spi_seq_item txn;

uvm_analysis_port #(spi_seq_item) spi_port;

function new(string name=“spi_monitor”,uvm_component parent);
super.new(name,parent);
endfunction

virtual function void build_phase(uvm_phase phase);
//super.build_phase(phase);
spi_port = new(“spi_port”,this);
if (! uvm_config_db #(virtual wb_intf) :: get (this, “”, “vif”, vif))
`uvm_fatal (get_type_name (), “Didn’t get handle to virtual spi interface in monitor”)
endfunction

virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
txn=spi_seq_item::type_id::create(“txn”,this);
uvm_info( get_type_name(), "Going to collect spi seq item sample in monitor", UVM_MEDIUM) forever begin collect_data(); uvm_info( get_type_name(), “spi seq item sample collected in monitor”, UVM_MEDIUM)
spi_port.write(txn);
end
endtask

task collect_data();
//#20;
txn.ss_pad_o=vif.`MON.ss_pad_o;

wait(vif.MON.wb_adr_i=='h10) //CTRL REGISTER ADDRESS begin if(vif.MON.wb_dat_i[8]) //GO_BSY==1
begin

//for lsb=1
if (vif.`MON.wb_dat_i[11]==1) //LSB will go first from miso
begin

	//tx_neg=0 [10](mosi=rising edge) rx_neg=1 [9](miso falling edge)

		if(vif.`MON.wb_dat_i[9]==1 && vif.`MON.wb_dat_i[10]==0)
		begin
			if(vif.`MON.wb_dat_i[6:0]==0)  //CHAR LEN==0
			begin
			int x=0;
				repeat(128)
				begin
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_miso[x]=vif.`MON.miso_pad_i;
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[x]=vif.`MON.mosi_pad_o;
				x++;
				end
			end
			
			if(!vif.`MON.wb_dat_i[6:0]==0) //CHAR LEN !=0
			begin
				for(int i=0;i<vif.`MON.wb_dat_i[6:0];i++)
				begin
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_miso[i]=vif.`MON.miso_pad_i;
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[i]=vif.`MON.mosi_pad_o;
				end
				
			end
		end
	
	//tx_neg=1 [10](mosi= negedge) rx_neg=0 [9](miso posedge)
	
	if(vif.`MON.wb_dat_i[9]==0 && vif.`MON.wb_dat_i[10]==1) 
		begin
			if(vif.`MON.wb_dat_i[6:0]==0)  //CHAR LEN==0
			begin
			int x=0;
				repeat(128)
				begin
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_miso[x]=vif.`MON.miso_pad_i;
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[x]=vif.`MON.mosi_pad_o;	
				x++;
				end
			end
			
			if(!vif.`MON.wb_dat_i[6:0]==0) //CHAR LEN !=0
			begin
				for(int i=0;i<vif.`MON.wb_dat_i[6:0];i++)
				begin
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_miso[i]=vif.`MON.miso_pad_i;
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[i]=vif.`MON.mosi_pad_o;	
				end
			end
		end

end //LSB=1 end

//if LSB=0

if (vif.`MON.wb_dat_i[11]==0) //MSB will go first from miso
begin

	//tx_neg=0 [10](mosi=posedge) rx_neg=1 [9](miso negedge)
	if(vif.`MON.wb_dat_i[9]==1 && vif.`MON.wb_dat_i[10]==0) 
		begin
			if(vif.`MON.wb_dat_i[6:0]==0)  //CHAR LEN==0
			begin
			int x=127;
				repeat(128)
				begin	
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_miso[x]=vif.`MON.miso_pad_i;
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[x]=vif.`MON.mosi_pad_o;	
				x--;
				end
			end
			
			if(!vif.`MON.wb_dat_i[6:0]==0) //CHAR LEN !=0
			begin

				for(int i=vif.`MON.wb_dat_i[6:0];i>0;i--)
				begin
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_miso[i]=vif.`MON.miso_pad_i;
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[i]=vif.`MON.mosi_pad_o;	
				end
			end
		end
	
	//tx_neg=1 [10](mosi= posedge) rx_neg=0 [9](miso negedge)
	if(vif.`MON.wb_dat_i[9]==0 && vif.`MON.wb_dat_i[10]==1)
		begin
			if(vif.`MON.wb_dat_i[6:0]==0)  //CHAR LEN==0
			begin
			int x=127;
				repeat(128)
				begin
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_miso[x]=vif.`MON.miso_pad_i;
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[x]=vif.`MON.mosi_pad_o;	
				x--;
				end
			end
			
			if(!vif.`MON.wb_dat_i[6:0]==0) //CHAR LEN !=0
			begin

				for(int i=vif.`MON.wb_dat_i[6:0];i>0;i--)
				begin
				@(negedge vif.`MON.sclk_pad_o)
				txn.spi_miso[i]=vif.`MON.miso_pad_i;
				@(posedge vif.`MON.sclk_pad_o)
				txn.spi_mosi[i]=vif.`MON.mosi_pad_o;	
				end
			end
		end

end //LSB=0 end
end //GO BSY end
end //CTRL end
endtask

endclass

6

In reply to kathula venkatesh:

Could you please paste from your simulation log-file what comes befor the monitor loop.

In collect_data I’d insert a few uvm_infos for debugging use.