Hello all,
I m working on uvm. In driver class, I am getting packets and then I need to convert each byte of each packet in 10 bits by using 8b10b encoder. These 10bits are then need to be converted from parallel to serial bacause the DUT takes input serially. I am confused how to tackle these tasks. I am hoping that 8b10b encoder and parallel in serial out(piso) to use as virtual tasks which can be called during the run phase() of driver, right? Please correct me anyone, if I am wrong?
Also how to pass the output of 8b10b encoder, the 10 bits, to PISO? Can the output of one task can be given to input of another/next task, just like that, i mean with no real problem? Or how else I should put these two tasks properly in driver class? Any help is appreciated.
Thanks,
Swapnil
Hello All,
I m still waiting for the answer for above mentioned querry. It will be great if somebody can throw some light on it as I am not able to get the proper path on how to proceed further. Any help would be appreciated.
Thanks,
Swapnil
How about something like the following in your driver:
task run_phase(uvm_phase phase);
data_seq_item req;
bit[9:0] data;
forever begin
seq_item_port.get_next_item(req);
data = convert_to_8b10b(req.data); // Function call to do the 8b10b conversion
// PISO code - clocked by the virtual interface - or you call a task that
// does the PISO taking data as the input.
seq_item_port.item_done();
end
endtask: run_phase
function bit[9:0] convert_to_8b10b(bit[7:0] data);
// Conversion function
endfunction: convert_to_8b10b
In reply to mperyer:
Hello mperyer,
I tried to use two tasks, one for 8b10b encoder and another for PISO. And called them during the run_phase() of driver. But while giving the output (10bits) of encoder, as an input to the PISO, it gives me compilation errors, shown below:-
** Error: driver4.sv(166): Illegal declaration after the statement near line ‘61’. Declarations must precede statements. Look for stray semicolons.
** Error: driver4.sv(175): Illegal declaration after the statement near line ‘170’. Declarations must precede statements. Look for stray semicolons.
I am not able get rid of these errors. I am thinking I am not passing the values i.e. those 10bits (output of encoder) properly to the PISO task? Can u plz give some guidance here.
Thanks,
Swapnil
You will have to share your code for me to be able to give specific feedback.
The most likely cause of the error message is that you are not declaring all of your variables before any statements - I’m guessing that you repeat the same mistake in both of your tasks.
You are not trying to do anything unusual. I would code the conversion to 8b10b as a function call, since this does not need to consume time.
In reply to mperyer:
Hello mperyer,
Thanks for your help. Please see the driver code below and please give me your feedback and where the code can be corrected:-
The error I am getting is: Error: driver41.sv(152): Illegal declaration after the statement near line ‘54’. Declarations must precede statements. Look for stray semicolons.
Driver class code:-
class driver extends uvm_driver #(transaction);
`uvm_component_utils(driver)
virtual dut_if dut_vi;
//constructor by using keyword new
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
assert( uvm_config_db #(virtual dut_if)::get(this, "", "dut_vi", dut_vi) );
endfunction : build_phase
virtual task run_phase(uvm_phase phase);
forever
begin
transaction tx;
reg dataout[];
forever begin
seq_item_port.get(tx);
// @(dut_vi.clock);
encode(tx);
@(dut_vi.clock);
pisov(dataout);
@(dut_vi.clock);
seq_item_port.item_done();
end
end
endtask: run_phase
virtual function encode (transaction tx) ;
byte unsigned bytes[];
int pkt_len;
// logic dispout ;
pkt_len = tx.pack_bytes(bytes);
uvm_report_info(get_full_name(),"Encoding 8bits in 10bits ...",UVM_LOW);
foreach (bytes[j])
begin
reg [8:0] datain;
bit dispin = 1; //0 = neg disp; 1 = pos disp
//bit ki;
//reg [8:0]
datain = bytes[j]; // <= look here the change
reg [9:0]dataout;
logic ai = datain[0] ;
logic bi = datain[1] ;
logic ci = datain[2] ;
logic di = datain[3] ;
logic ei = datain[4] ;
logic fi = datain[5] ;
logic gi = datain[6] ;
logic hi = datain[7] ;
logic ki = datain[8] ;
logic aeqb = (ai & bi) | (!ai & !bi) ;
logic ceqd = (ci & di) | (!ci & !di) ;
logic l22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
logic l40 = ai & bi & ci & di ;
logic l04 = !ai & !bi & !ci & !di ;
logic l13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
logic l31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
logic ao = ai ;
logic bo = (bi & !l40) | l04 ;
logic co = l04 | ci | (ei & di & !ci & !bi & !ai) ;
logic d0 = di & ! (ai & bi & ci) ;
logic eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ;
logic io = (l22 & !ei) |
(ei & !di & !ci & !(ai&bi)) | // D16, D17, D18
(ei & l40) |
(ki & ei & di & ci & !bi & !ai) | // K.28
(ei & !di & ci & !bi & !ai) ;
// pds16 indicates cases where d-1 is assumed + to get our encoded value
logic pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ;
// nds16 indicates cases where d-1 is assumed - to get our encoded value
logic nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ;
// ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
logic ndos6 = pd1s6 ;
// pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
logic pdos6 = ki | (ei & !l22 & !l13) ;
// some Dx.7 and all Kx.7 cases result in run length of 5 case unless
// an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
// specifically, D11, D13, D14, D17, D18, D19.
logic alt7 = fi & gi & hi & (ki |
(dispin ? (!ei & di & l31) : (ei & !di & l13))) ;
logic fo = fi & ! alt7 ;
logic go = gi | (!fi & !gi & !hi) ;
logic ho = hi ;
logic jo = (!hi & (gi ^ fi)) | alt7 ;
// nd1s4 is cases where d-1 is assumed - to get our encoded value
logic nd1s4 = fi & gi ;
// pd1s4 is cases where d-1 is assumed + to get our encoded value
logic pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ;
// ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
logic ndos4 = (!fi & !gi) ;
// pdos4 is nd1s4 cases where d-1 is - yields + disp out
logic pdos4 = fi & gi & hi ;
// only legal K codes are K28.0->.7, K23/27/29/30.7
// K28.0->7 is ei=di=ci=1,bi=ai=0
// K23 is 10111
// K27 is 11011
// K29 is 11101
// K30 is 11110 - so K23/27/29/30 are ei & l31
logic illegalk = ki &
(ai | bi | !ci | !di | !ei) & // not K28.0->7
(!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7
// now determine whether to do the complementing
// complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
logic compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ;
// disparity out of 5b6b is disp in with pdso6 and ndso6
// pds16 indicates cases where d-1 is assumed + to get our encoded value
// ndos6 is cases where d-1 is + yields - disp out
// nds16 indicates cases where d-1 is assumed - to get our encoded value
// pdos6 is cases where d-1 is - yields + disp out
// disp toggles in all ndis16 cases, and all but that 1 nds16 case
logic disp6 = dispin ^ (ndos6 | pdos6) ;
logic compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ;
//assign
logic dispout = disp6 ^(ndos4 | pdos4) ;
//assign
dataout = { >> {(jo ^ compls4), (ho ^ compls4),
(go ^ compls4), (fo ^ compls4),
(io ^ compls6), (eo ^ compls6),
(d0 ^ compls6), (co ^ compls6),
(bo ^ compls6), (ao ^ compls6)}};
end
endfunction : encode
virtual task pisov(dataout); // dataout is the output of encoder,mentioned in encode function
reg dataout[];
int pkt_len;
bit enable;
bit ser_OUTPUT;
// pkt_len = tx.pack_bytes(bytes);
uvm_report_info(get_full_name(),"Driving 10bits and convering to serial bitstream ....",UVM_NONE);
foreach (dataout[k])
begin
reg [9:0] load;
reg [8:0] counter = 0;
dut_vi.DIGRF_CLK_OE <= 0;
@(dut_vi.clock)
dut_vi.DIGRF_CLK_OE <= 1;
load=dataout[k];
if (dut_vi.DIGRF_CLK_OE==1'b1 && counter<9)
begin
load=load[0] & load[8:1];
counter=counter+1;
end
ser_OUTPUT=load[0]; //this needs to be connected to serial line of DUT
end
@(dut_vi.clock)
dut_vi.RXN_IN[0] <= ~ser_OUTPUT;
dut_vi.RXP_IN[0] <= ser_OUTPUT;
endtask : pisov
endclass: driver
Thanks for your help,I appreciate that.
Swapnil
In reply to swapnilm:
Verilog as well as SystemVerilog has a requirement that in any procedural block, all declarations must come before and procedural statement, like an assignment statement. So follow the advice of the error message.