Helo with TLM Explanation and Examples?

UVM
1

hi,
Iam new to uvm
i didn’t able to get port,import,export,implementation,analysis?

initiator,target,producer consumer
someone help me with with explanation and example
thank you

2

In reply to sudharshan:

https://verificationacademy.com/cookbook/analysisport
https://verificationacademy.com/sessions/how-tlm-works

3

In reply to sudharshan:

hi,
Iam new to uvm
i didn’t able to get port,import,export,implementation,analysis?
initiator,target,producer consumer
someone help me with with explanation and example
thank you

Sudharshan,

There are a number of examples in the UVM-Connect package showing
producers as TLM2 intiators, consumers as TLM2 targets,
and analysis ports.

Most of these examples are centered around cross-language
(SystemC, SystemVerilog) TLM connections. However, there are
one or two examples showing just native SystemVerilog connections.

Additionally there’s a fairly good “TLM primer” that comes
with the UVM-Connect documentation (see docs/html/index.html
docs/UvmConnectPrimer, or docs/TLM_REVIEW.txt).

Specifically an example you can start with is examples/connections/sv2sv_native.sv).

You’ll find the last-released UVM-Connect v2.3.1 package on this
Verification Academy.

– johnS

4

In reply to dave_59:

thanks dave…