In the below code getting output as 0 instead of 32’hFFFFFFF. Correct me if did mistake. Please provide your comments.
Code Explanation:
Assigning 32’hFFFF_FFFF to variable b @ first posedge of clk
Assigning 0 to variable a @ 5th posedge of clk using hdl path(plz discard syntax error)
Assigning 32’hFFFF_FFFF to variable b @ 7th posedge of clk
Displaying the value of b @ 11th posedge of clk
Module hdl_deposit_check();
Logic[31:0] a;
Wire[31:0] b;
assign a=b;
initial
begin
b=0;
@(posedge clk)
b <= 32’hFFFF_FFFF;
repeat(6) @(posedge clk);
b <= 32’hFFFF_FFFF;
repeat(4) @(posedge clk);
$display(“Result :- %x”,a);
end
initial
begin
repeat(4) @(posedge clk);
hdl_deposit(a,32’h0); // using hdl deposit ,depositing value “0” to variable a
end
endmodule
Hi Dave,
Sorry for the inconvenience.logged in via mobile. Having problem with laptop. Updated code is shared below
In the below code getting output as 0 instead of 32’hFFFFFFF. Correct me if did mistake. Please provide your comments.
Code Explanation:
Assigning 32’hFFFF_FFFF to variable b @ first posedge of clk
Assigning 0 to variable a @ 5th posedge of clk using hdl path(plz discard syntax error)
Assigning 32’hFFFF_FFFF to variable b @ 7th posedge of clk
Displaying the value of b @ 11th posedge of clk
module hdl_deposit_check(input clk);
logic[31:0] a;
wire[31:0] b;
assign a=b;
initial
begin
b=0;
@(posedge clk)
b <= 32'hFFFF_FFFF;
repeat(6) @(posedge clk);
b <= 32'hFFFF_FFFF;
repeat(4) @(posedge clk);
$display("Result :- %x",a);
end
endmodule
module top();
logic clk;
string path="top.dut.a";
hdl_deposit_check dut(clk);
initial
begin
clk=0
repeat(4) @(posedge clk);
uvm_hdl_deposit(path,32'h0); // using hdl deposit ,depositing value ?0? to variable a
end
initial
forever #5 clk++
endmodule
OK, now it is a little more clear that you are using the backdoor uvm_hdl_deposit function from the UVM package. That function acts like a procedural assignment to ‘a’. This is a good example why SystemVerilog does not allow mixing procedural and continuous assignments to the same variable.
Continuous assignments are sensitive to changes in the operands on the RHS. With any change, the RHS expression gets evaluated and updates the LHS. Your testcase never changes ‘b’ after calling uvm_hdl_deposit to make a backdoor procedural assignment to ‘a’. So the continuous assignment **assign a = b** never has a chance to evaluate the RHS.
You should be using uvm_hdl_force and uvm_hdl_release.