Have a problem using peek method

UVM
1

I can not read the register hardware value via peek method.
DUT has ram type register(16*32). we try to read the hardware ram type register via the uvm register model.
there is no external address but just fifo type.
error message is UVM_ERROR: get: unable to locate hdl path top_tb.fdo.rx_fifo_ram[0]
Either the name is incorrect, or you may not have PLI/ACC visibility to that name.

2

There is not nearly enough information to help you here.

Do you understand how to get PLI/ACC access to the register? It’s the same as being able to display it in a waveform window. Can you do that?

Is it only this register you are having a problem with? Does it work with any other backdoor register access?

3

In reply to dave_59:

thanks for your answer.

I’m verifying my DUT using uvm register model backdoor access.

here, I find my problem.

My DUT is designed by VHDL code.

but, SPI master example is verilog code.

for instance, SPI master model back door access use reg type signal called “ctrl”.
and The “ctrl” is used for HDL path for backdoor access.

but, my VHDL DUT code is declared as below.

type ram_type is array (31 downto 0) of std_logic_vector(15 downto 0);
signal rx_fifo_ram : ram_type;

here, i made uvm rx0 register of rx_fifo_ram[0].
uvm rx1 register >> rx_fifo_ram[1]
uvm rx2 register >> rx_fifo_ram[2]
.
.
.
uvm rx31 register >> rx_fifo_ram[31]

then, i added these registers inside build method in register block.

and i added hdl path as below.

rx0_reg.add_hdl_path_slice(“rx_fifo_ram[0]”, 0, 16);
rx1_reg.add_hdl_path_slice(“rx_fifo_ram[1]”, 0, 16);
.
.
rx31_reg.add_hdl_path_slice(“rx_fifo_ram[31]”, 0, 16);

finally, this way is not executed.

how can i do this?

4

Which version of Questa are you using?

Are you using the built-in version of the UVM?

5

In reply to mperyer:

i use 6.6d version.

so UVM is not built-in, i manually compiled it.

6

Support for VHDL backdoor is not part of the UVM since it is vendor dependent. Support for VHDL backdoor access was added to Questa at around 10.1b.

You have two choices - upgrade your Questa version to the latest, or contact Mentor Support to get the uvm_hdl.c file from the $QUESTA_HOME/verilog_src/uvm_1.1a/src/dpi directory.

If you take the uvm_hdl.c route, you will then have to copy this over the equivalent file in $UVM_HOME/src/dpi, then compile uvm_dpi on your platform via the Makefile in the UVM examples directory to get a shared object.

7

In reply to mperyer:

Thanks. But i upgrade uvm_hdl.c file to quesatsim10.1 version. But it is not solved yet. Do you know another solution?

8

In reply to BAEILHO:

Hi BAEILHO,
I am also facing same issue. If you have any solution please let me know.