Handling on the fly reset in scorebaord

UVM
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1

Hi,

What is the best way of handling on the fly reset (reset when transaction is in progress) in UVM-scoreboard. There may be n methods. what would be the best method.

Thanks
Saravanan

2

In reply to saravanantvs:

The question is what kind of reset you are doing. Do you have a reset sequence? Or how do you generate a reset.

3

In reply to chr_sue:

Hi,

Assume it is block level verification enviroment. And i want to test, whether the rtl is able come out of reset(like statemachine_state = IDLE, fifo read ptr and write ptr are reset to zero ). Could you please suggest best method to do it.

4

In reply to saravanantvs:

The level does not matter. The best way to identify the reset has consequences is using SV concurrent assertions.
But your first question was differently.

5

In reply to chr_sue:

My Question is about scoreboard not about assertion.

6

In reply to saravanantvs:

This link may be useful http://cfs-vision.com/2016/04/18/systemverilog-how-to-handle-reset-in-uvm/

HTH,

R

7

In reply to rgarcia07:

We/I make use of the UVM phases-- one of which is reset_phase.

The reset tests will actually jump backwards from the main_phase (or other phases) to the reset phase. The scoreboard is aware of the phasing-- so you can handle stuff there. For example, if you have two queues (one for actual, one for expected), you can clear them in the reset phase.

I find this to be very clean.

8

In reply to wpiman:

In reply to rgarcia07:
We/I make use of the UVM phases-- one of which is reset_phase.
The reset tests will actually jump backwards from the main_phase (or other phases) to the reset phase. The scoreboard is aware of the phasing-- so you can handle stuff there. For example, if you have two queues (one for actual, one for expected), you can clear them in the reset phase.
I find this to be very clean.

You are discussing about undefined things. If the questioner is not explaining what his problem is it does not make sense to answer.
Does the questioner want to flush the analysis fifos or what does he expect. Is it only a simple asynchronous reset or what is it.

9

You are discussing about undefined things. If the questioner is not explaining what his problem is it does not make sense to answer.
Does the questioner want to flush the analysis fifos or what does he expect. Is it only a simple asynchronous reset or what is it.

I don’t follow your logic.

He asked about best practices-- he didn’t actually state a particular problem.

saravanantvs: Take a look at this paper from SNUG. It gives a good description of using UVM phases and phase jumps to do reset testing. Should give you a place to start.

http://www.sunburst-design.com/papers/HunterSNUGSV_UVM_Resets_paper.pdf