Guidelines to takecare when integrating UVM Env for Module to SoC Level

UVM
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Hi All,
Are there any specific guidelines one needs to take care when integrating a UVM Environment for a Module, which is now part of a larger SoC.

What issues typically one can encounter?
What are the changes required, How Re-usability of the Environment can be helpfull?
What configuration changes may be required to ensure that few cases can be run at SoC level for this piece of UVC integrated.

Thanks,
Ravi

2

In reply to ravi.gupta:

Hi All,
Are there any specific guidelines one needs to take care when integrating a UVM Environment for a Module, which is now part of a larger SoC.
What issues typically one can encounter?
What are the changes required, How Re-usability of the Environment can be helpfull?
What configuration changes may be required to ensure that few cases can be run at SoC level for this piece of UVC integrated.
Thanks,
Ravi

There are 2 parts to this.

  1. the guidelines to follow when developing the block level TB such that it is usable at the next level (AKA vertical re-use)
  2. the guidelines to follow when instantiating such a TB at SoC or sub-system level

This topic is well covered in UVM cookbook.