Getting issues in Compiling UVM Hello world code in Questasim10.3d

UVM
,
1

What steps i need to follow to make UVM code to get simulated in Questasim.

I found uvm1.1c library available at tool installed path but it is not getting compiled.

Do i need to pass any switch to vlog command.

Iam getting errors as below:
vlog -sv top.sv
** Error: top.sv(1): Cannot open include file "/tools/qsim-10.3d/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/uvm_pkg.sv". -- Compiling module top -- Importing package uvm_pkg (uvm-1.1d Built-in) ** Error: top.sv(5): (vlog-2163) Macro uvm_component_utils is undefined.
** Error: top.sv(5): near “(”: syntax error, unexpected ‘(’, expecting function or task
** Error: top.sv(7): near “new”: syntax error, unexpected new, expecting TYPE_IDENTIFIER
** Error: top.sv(11): (vlog-2163) Macro uvm_info is undefined. ** Error: top.sv(15): (vlog-2163) Macro uvm_info is undefined.
** Error: top.sv(17): near “end”: syntax error, unexpected end
End time: 18:46:32 on Aug 17,2015, Elapsed time: 0:00:00

I can see it is pointing to OVM Library but someone should help me to select the switch to pass UVM Library.
Thanks
Bharath

2

In reply to bharath123:

All,

By having below two commands i could create library and compile the uvm pkg,my uvm code.

vlib work
vlog -sv top.sv +incdir+/tools/qsim-10.3d/verilog_src/uvm-1.1d/src

Iam getting Elaboration error…

How should i pass dpi?

If i use below command
vsim work.top +UVM_TEST_NAME=ahb_uvm_test -sv_lib=/tools/qsim-10.3d/verilog_src/uvm-1.1d/src/dpi/uvm_dpi.svh

Iam getting errors:

Failed to find user specified function ‘uvm_hdl_check_path’ in DPI C/C++ source files.

Time: 0 ns Iteration: 0 Region: /uvm_pkg File: /tools/qsim-10.3d/verilog_src/uvm-1.1d/src/uvm_pkg.sv

Someone help me to fix this issue.

Thanks

3

Most SystemVerilog simulators come with the UVM completely pre-compiled - there should be no need to put any switches or files on the command line for the UVM source code. All you need to do is put import uvm_pkg::*; and `include “uvm_macros.svh” in your source files. See http://go.mentor.com/uvm1-0-questa

4

In reply to dave_59:

Please find my code below

////////////////////////////////////////////////////////////////////////////
include "uvm_pkg.sv" include “uvm_macros.svh”
module top;
import uvm_pkg::*;
class ahb_uvm_test extends uvm_test;
uvm_component_utils(ahb_uvm_test) function new(string name,uvm_component parent); super.new(name,parent); endfunction //task run_phase(uvm_phase phase);' task run_phase(uvm_phase phase); uvm_info(“TEST”,“In test run phase”,UVM_LOW);
endtask
endclass
initial begin
`uvm_info(“TOP”,“Simulating the test”,UVM_LOW);
run_test(“ahb_uvm_test”);
end
endmodule
////////////////////////////////////////////////////////////////
My command:
vsim work.top +UVM_TEST_NAME=ahb_uvm_test -L /tools/qsim-10.3d/verilog_src/uvm-1.1d

I am getting below issue
Error: (vopt-19) Failed to access library ‘/tools/qsim-10.3d/verilog_src/uvm-1.1d’ at “/tools/qsim-10.3d/verilog_src/uvm-1.1d”.

Thanks
Bharath

5

In reply to bharath123:

This forum is not really for tool specific help, but as I said previously, there should be no need to put any switches or files on the command line for the UVM source code, so remove the “-L /tools/qsim-10.3d/verilog_src/uvm-1.1d” and remove any UVM switches for vlog as well.

6

In reply to dave_59:

Dave,

I Guess i dont have the Precompiled UVM Libraries available.

Ok thanks i will check with the support team.

Bharath