Getting an error name : Expecting the keyword 'endclass'

I just tried compiling my testbench. Compiled all the necessary files using make file by including it in a .f file. But when it comes to compiling the testbench it is showing the above mentioned error. Can anyone tell me whats wrong?

include "uvm_macros.svh" 2 import uvm_pkg::* ; -----CODE----- 12 module tb(); 13 logic clk; 14 d_ff_intf vif(clk); 15 d_ff dut(.clk(clk),.rst(vif.rst),.d(vif.d),.q(vif.q)); 16 17 initial 18 clk = 1'b0; 19 20 always begin 21 forever 22 #5 clk = ~clk; 23 end 24 25 initial begin 26 uvm_config_db#(virtual d_ff_intf)::set(null,"*","d_ff_intf",vif); 27 uvm_info(“TOP”,“Set the interface from the top”,UVM_LOW);
28 run_test(“d_ff_test”);
29 #200;
30 $finish();
31 end
32
33 initial
34 begin
35 $dumpfile(“dff_tb.vcd”);
36 end
37
38 endmodule
39

In reply to kevin488:

There’s probably a problem with the file that compiles just before your testbench. Try to compile without the testbench file.