Getting around UVM/REG/DUPLROOT

UVM
, ,
1

Hi,

I am trying to get around this error in my environment.

The environment structure that I have with my register model look something like this (I rather want it to look like this).

  • env.sub_env[0].regmodel
  • env.sub_env[1].regmodel
  • env.sub_env[2].regmodel

{all "regmodel"s above are instances of the same registermodel class}

I am getting this error from UVM library since the register model instance names are all similar in all of the sub-environments. I look at the code and I see this. ( see uvm_reg_block.svh )

 // Check that root register models have unique names

  // Has this name has been checked before?
  if (m_roots[this] != 1) begin
     int n = 0;

     foreach (m_roots[_blk]) begin
        uvm_reg_block blk = _blk;

        if (blk.get_name() == get_name()) begin
           m_roots[blk] = 1;
           n++;
        end
     end

     if (n > 1) begin
      `uvm_error("UVM/REG/DUPLROOT",
                   $sformatf("There are %0d root register models named \"%s\". The names of the root register models have to be unique",
                             n, get_name()))
     end
  end

It does not make sense to me why we only look at the root name and not the full register model instance hierarchy? Can anyone pitch in here? If any of you know of a way to get around this, please let me know.

Thank you!

2

Facing same issue with my UVM ral test-bench.
Any solution to clean this error?
Thanks.

Regards,
Suhas N S

3

In reply to suhas.ns:

remove lock_model() call within your block. I don’t know the consequences.

4

In reply to badrip.nitt:
I’m not surE what you are doing. It works pretty fine, what your intention is.
My guess is you are considering your registermodel as a uvm_component, but it is a uvm_object and this is not visible in the component hierarchy.
Please check for this.

5

In reply to badrip.nitt:

Suggested way is to create a top level regblock which will contain these individual instances then pass the sub-block models to sub-envs.

class ral_top_block extends uvm_reg_block;
  ral_0 regmodel[3];
  virtual funciton void build();
      foreach(regmodel[i]) begin
        regmodel[i] = new($sformatf("regmodel%0d", i));
        regmodel[i].build();
      end
  endfunction
endclass

ral_top_block top_regmodel;
  top_regmodel = new("top_regmodel");
  subenv0.regmodel = top_regmodel.regmodel[0];
  subenv1.regmodel = top_regmodel.regmodel[1];

By following this approach we make sure that we will have only one top-level regmodel.

Another way is that you can create individual regmodel with unique names (in your test or top level env) and pass to sub-environments.

Hope it helps.