GETTING 13609 ERROR NOT REGISTERD with the class

UVM
,
1

** Error: (vlog-13069) C:/Users/shiva/Desktop/New folder/env_cfg.sv(1): near “uvm_object”: syntax error, unexpected IDENTIFIER.

** Error: C:/Users/shiva/Desktop/New folder/env_cfg.sv(1): Error in class extension specification.

this is the new error im getting …
previous error has been solved

this is my top

include "interface.sv" include “fifo.v”
`include “ram.v”

module top;
import uvm_pkg::*;
`include “uvm_macros.svh”

`include “fifopackages.svh”

bit clock;
//reg clock;
always
forever
begin
#5 clock=!clock;
end

fifo_interface vif(clock);
synch_fifo DUT( .clk(vif.clock),
.rst_in(vif.reset),
.wren_in(vif.wren_in),
.wrcs_in(vif.wrcs_in),
.rden_in(vif.rden_in),
.rdcs_in(vif.rdcs_in),
.data_in(vif.data_in),
.data_out(vif.data_out),
.full_out(vif.full_out),
.empty_out(vif.empty_out),
.ovr_flw(vif.overflow_out));

			initial begin
			uvm_config_db#(virtual fifo_interface)::set(null,"*","string1",vif);
			run_test();
			end

endmodule

this is my env_cfg

class env_cfg extends uvm_object;
`uvm_object_utils(env_cfg)

int has_wagt=1;
int has_ragt=1;

int has_sb;

function new(string name=“env_cfg”);
super.new(name);
endfunction

endclass

2

In reply to ram999:

Where are you compiling env_cfg or doi you include this also?
Looks like uv_object is not defined. This happens when you do not import the uvm_pkg.

3

In reply to chr_sue:

yes i included the env_pkg in fifopackage…
already imported in top pls check it…

still getting the same error

4

In reply to ram999:

You should always compile your packages as a separate compilation scope and then import them into your testbench. Do NOT `include them.

Try compiling fifopackages separately and see what errors you get.

5

this is my fifopackge
include "uvm_macros.svh" include “write_txn.sv”
include "wr_cfg.sv" include “rd_cfg.sv”

`include “env_cfg.sv”

include "wr_driver.sv" include “wr_monitor.sv”
include "wr_seqr.sv" include “wr_sequence.sv”
`include “wr_agt.sv”

include "read_xtn.sv" include “rd_driver.sv”
include "rd_monitor.sv" include “rd_seqr.sv”
include "rd_agt.sv" include “rd_sequence.sv”

include "fifo_env.sv"*/ include “fifo_test.sv”

6

In reply to ram999:

But you do not import the uvm_pkg.

7

In reply to chr_sue:

i dint understood …pls can you elabarate

8

In reply to ram999:

compiling a package with class-base code needs to things:
(1) import uvm_pkg::*;
(2) `include “uvm_macros.svh”

In your package you have only the include. The import statement is missing.

9

In reply to chr_sue:
Christoph, that is not the problem. They are importing umm_pkg in module top.

ram999, is the file “fifopackages.svh” a SystemVerilog package? A package declaration would not be allowed inside a module. Do the files that come just before env_cfg.sv contain any references to UVM classes?

You need to follow Chuck’s advice and put all your classes in a separate package, then compile them individually.

10

In reply to dave_59:

yes fifopackages are SV package …

i dint get dave …

11

In reply to ram999:

You need to compile your packages separately from your testbench:

vlog fifopackages.svh

Then in the top module, replace “`include fifopackages.svh” with “import fifopackages::*;”

Then compile your testbench:

vlog top.sv