Get_mirrored_value() mismatch

UVM
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1

According to the documentation, the mirrored value of a register is updated by the predictor at the end of a transaction. But what about before any register accesses? Here is the full scenario:

I have a register regA with reset value being non-zero (e.g. 0x1). The configure method reflects that correctly.

When I do get_mirrored_value() on regA before any actual reads/writes to it, for example right after reset, I get a data mismatch between the return of the function and the RTL actual data read back.

I believe the issue is initially the reset value of the registers/fields are not applied to the mirrored/desired values unless I explicitly call regA.reset(). Is that the expected behavior?

Is the expected use model for the user to call reset() after lock_model() or somewhere close? Maybe call reset() at the block level?

Thanks
-Bahaa

2

In reply to Bahaa Osman:

Hi!

  1. Did you reset your RTL?
  2. You should call regmodel.reset() when a physical reset is observed. Are you handling the reset in any way in your TB?

BR

3

In reply to nilaci:

Good question. This is happening at the beginning of the test, so the RLT just came out of reset. I was hoping that at time 0, somewhere in RAL, a reset is called to initialize the regmodel.

4

In reply to Bahaa Osman:

mirror value of the register isn’t updated until you read the register. To update the mirror values of all the registers same as their reset value, call the m_reg_model.reset() after dut reset or in reset phase.


	virtual task reset_phase (uvm_phase phase);
		..
		m_reg_model.reset();
		...
	endtask
5

In reply to Rahulkumar Patel:

Thanks both for the answers. I added the reset() call.