Hi
I understand that we can create a hierarchical register model, consisting of a cluster of register blocks, each of which correspond to a block in the hierarchy of our DUT. On the other hand, only the map in the top level register block is associated with a sequencer, which I can easily justify for myself. My question is that when something is written to a register inside a register block deep down in the hierarchy, what exactly happens to the register level transaction generated and HOW is it transferred to the top level register block to be sent to the driver via the sequencer? Does it happen automatically, considering that the sub-maps are added to the top level map? Or is there some more action required to deliver it to the top level?
Thanks
In reply to Farhad:
The address space is flat. The fact that the register blocks have offsets based on the hierarchical design of the DUT is inconsequential. the RAL model does not care how the design decodes the registers, but that is usually the way it works out.