Hi,
I have a question regarding generating and holding the clock as desired.
I know its quite wage let me stage it in detail below.
my sequence_item generates random values constraint in certain range for few variables.
In my driver sum of all, the above-generated values give me numClks-> this the number for which I want to generate clocks while driving my enable signal low.
Now, here is my question, there is another signal call hold which when generated my clocks should keep running but numClks should just be frozen till the hold is de-asserted.
Explaining the question using an example.
Assume numClks = 10.
driver asserts enable and start generating clk for 10 cycles, but sees the hold signal after 5 clocks generated for 100 ns.
thus, the driver should keep driving the clk at the interface for 100 ns but should not account for decrementing of numClks post 100ns it should start decrementing numClks and generate 5 more remaining clks.
I am trying to accomplish the above using event and trigger, but not able to achieve the desired result in the waveform.
Any idea or approach will greatly be appreciated.
Please let me know, I can share my pseudo code if desired.
Thanks & Regards,
Piyush
