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  • function problem

function problem

UVM 6941
peter
peter
Full Access
164 posts
April 29, 2022 at 9:21 am

Hi All
build phase, connect phase, run phase are virtual function/task. What are the problem if build/run/connect phase are not virtual?
I am a bit confused
Thanks!

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dave_59
dave_59
Forum Moderator
11276 posts
April 29, 2022 at 10:21 am

In reply to peter:

These phase methods are defined as virtual functions/tasks in the UVM base class uvm_component. Once declared virtual, they are always virtual in all derived class method overrides. This is regardless of using the virtual keyword in the function task overrides, they are still virtual methods because of the base class definition.

If you are having trouble understanding how virtual methods work, please see my SystemVerilog OOP for UVM Verification.

— Dave Rich, Verification Architect, Siemens EDA

peter
peter
Full Access
164 posts
April 29, 2022 at 7:18 pm

In reply to dave_59:
As for build/connect phase,
it seems that we do not assign derived class to base class in the beginning. So,is it necessary to define virtual?
Thanks

dave_59
dave_59
Forum Moderator
11276 posts
April 29, 2022 at 7:48 pm

In reply to peter:

See the virtual print method in the second session of my SystemVerilog OOP for UVM Verification presentation.

print() is being called from a base class variable.

— Dave Rich, Verification Architect, Siemens EDA

peter
peter
Full Access
164 posts
April 29, 2022 at 9:28 pm

In reply to dave_59:

thank for reply . Would you tell me what are problems if phase methods are defined as non-virtual in the uvm_component ?

dave_59
dave_59
Forum Moderator
11276 posts
April 30, 2022 at 9:41 am

In reply to peter:

Suggest you look at this video and example code and see what happens when you remove the virtual keyword.

— Dave Rich, Verification Architect, Siemens EDA

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