My question is if there is a DUT and it has a FSM, How can I build a reference model to verify the FSM inside the DUT. Is there a good approach besides using assertion
In reply to Chandler:
There’s no need to build a reference model of an FSM. You need to build a reference model of the requirements the FSM was designed for.
There are many tools out there that check the validity of the FSM (all states reachable, no deadlocks, etc) without you have to write any models.