Forcing a vif.signal from a v_sequence

Hello,
if have a following virtual interface:

interface ifu_int_if;
logic porta_tx_rdy;
task shutdown_rdy();
force porta_tx_rdy = 1’b0;
endtask : shutdown_rdy
task release_mac_ready();
release porta_tx_rdy;
endtask : release_mac_ready
endinterface : ifu_int_if

I would like to force/release the vif.signal from within a sequence:
class ifu_tx_v_sequence extends ifu_base_v_sequence;
`uvm_object_utils(ifu_tx_v_sequence) // ifu_int_if is instaned in p_sequncer
task body();
shutdown_mac();
endtask : body

task shutdown_mac();
        p_sequencer.int_vif.shutdown_rdy();
        @(posedge p_sequencer.int_vif.mac_div2); // confirm there is no sop in following cycle
        repeat(500)@(posedge p_sequencer.int_vif.mac_div2);
        p_sequencer.int_vif.release_mac_ready();
endtask : shutdown_mac

endclass: ifu_tx_v_sequence

i see that the sim pointer does reach the force/release tasks, but the force is not taking place.
Any idea what am i doing wrong?
the objective is to be able to force/release a signal inside a body of a stimuli sequence.

Thank you

In reply to tsafrirw:

It is strongly recommended that you don’t do any signal access from a sequence. You should create the appropriate sequence_item()/driver task to accomplish your goal.

The reason for this is that by limiting signal access to only the driver, you reduce the potential for signal conflicts coming from many different locations.

You didn’t mention if you are seeing X’s, undefined signals or something else, but I would suspect that you have conflicts somewhere.

In reply to tsafrirw:

@tsafrirw:
I believe you do not understand what the benefits of TLM are. What you want to do is something what should happen inside the driver. Because the transaction does not have a relationship with respect to clock cycles it is impossible to do this from a sequence. The sequence generates untimed seq_items.

chr_sue,
I totally understand the concept of TLM. notice I call a task within the virtual interface. I figured out why it is not working.
the 'force must be done on the full path of the DUT signal and not its vif assignment as it can only probe a signal but not force/release it as explained in Dave’s article:
https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection