$finish called by verilog testbemch - integrating with UVM

Question

We are integrating a UVM verification env into an existing verilog testbench infrastructure where the master is the chip CPU
i.e when the CPU finishes running the commands the test closes down.
We would like to delay the UVM testbench from closing down but still receive the UVM report in the log.
We cannot delay in final_phase because it is a function. If delayed in shutdown_phase we do not get the uvm report.
Adding a phase seems like too much overhead
Any suggestions ?

Answer 1

dave_59

Forum Moderator

10504 posts

January 19, 2016 at 8:53 pm

In reply to meir:

You will need to modify your Verilog testbench to raise_objection() at the beginning of the test, and then replace the call to $finish with a drop_objection(). I'm not sure if you can raise an objection to ending a phase before that phase starts, so you may want to just use the run_phase.

— Dave Rich, Verification Architect, Siemens EDA

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