Hi All
Can any one tell me is the final phase is top down or bottom up ,
some where i have studied final phase is top down ?
Can any one please clarify me
The final_phase() is a top-down phase, like build_phase(). All others are bottom-up.
For normal UVM flows the final_phase() is not required / left empty and you should do any end-of-test reporting in your report_phase() and ignore final_phase().
The final_phase() exists in UVM only for arrangements which run multiple loops around run…extract…check…report phases in a loop and then jump back to run() for the next iteration of multiple concatenated tests. Support for this is only partially defined or implemented in UVM today and is unlikely to be widely used in the industry (I would not recommend it for any use model that I am aware of).
However if this technique is used, there is a need for a final_phase() which is guaranteed to be the last phase before simulation exits, unlike report_phase() which may loop back. Why top-down? If one used this looped multiple test arrangement, final_phase() would be used for any cleanup required outside the loop, and hence it is top down, to ensure control from the topmost level of your test environment of that multiple test loop.
% grep -r ‘class.extends uvm_._phase’ .
./base/uvm_common_phases.svh:class uvm_build_phase extends uvm_topdown_phase;
./base/uvm_common_phases.svh:class uvm_connect_phase extends uvm_bottomup_phase;
./base/uvm_common_phases.svh:class uvm_end_of_elaboration_phase extends uvm_bottomup_phase;
./base/uvm_common_phases.svh:class uvm_start_of_simulation_phase extends uvm_bottomup_phase;
./base/uvm_common_phases.svh:class uvm_run_phase extends uvm_task_phase;
./base/uvm_common_phases.svh:class uvm_extract_phase extends uvm_bottomup_phase;
./base/uvm_common_phases.svh:class uvm_check_phase extends uvm_bottomup_phase;
./base/uvm_common_phases.svh:class uvm_report_phase extends uvm_bottomup_phase;
./base/uvm_common_phases.svh:class uvm_final_phase extends uvm_topdown_phase;
./base/uvm_runtime_phases.svh:class uvm_pre_reset_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_reset_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_post_reset_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_pre_configure_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_configure_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_post_configure_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_pre_main_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_main_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_post_main_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_pre_shutdown_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_shutdown_phase extends uvm_task_phase;
./base/uvm_runtime_phases.svh:class uvm_post_shutdown_phase extends uvm_task_phase;
Summary: final_phase() is mostly never required, don’t use it.
In reply to gordon:
Hi Gordon,
I have a case where I’m verifying a DUT which involves a lot of common initialization (reg config). In this case I wan’t to use this approach of multiple tests run one after the other. I can’t merge the test-logic into 1 single test as it becomes very clumsy.
When you say, final_phase() is not very well defined, is it deprecated ? Also, how do I specify the multiple tests to the simulator and govern the order in this case?
-Thanks