Fatal: (SIGSEGV) Bad handle or reference

Hi
I am doing factory override example that how to override it
but i have got error Bad handle or reference. please tell me why is that coming and where

code:-

include "uvm_macros.svh" import uvm_pkg::*; class pkt extends uvm_sequence_item; uvm_object_utils(pkt)
rand bit [3:0] a;
rand bit [3:0]b;

 function new(string name="pkt");
	 super.new(name);
 endfunction
  
  
  function void display(string c);
    
    
     $display("a=%d,b=%d c=%s",a,b,c);
   endfunction
   
    endclass
  
  
  
  
  class prod extends uvm_component ;
`uvm_component_utils(prod)


 

 function new(string name="",uvm_component parent);
	 super.new(name,parent);
	 endfunction
	 
 
 pkt p;
 prod pr;
 uvm_blocking_put_port #(pkt) put_port;
 
 function void build_phase(uvm_phase phase);
   put_port=new("put_port",this);
   pr=prod::type_id::create("pr",this);
   endfunction
   
   
   task run_phase(uvm_phase phase);
     
     repeat(3)
     begin
     p=pkt::type_id::create("p");
     assert(p.randomize()with {p.a>1;p.b==10;});
    p.display("prod");
    
    
     put_port.put(p);
     end
     
     endtask
  endclass
  
  
  class prod1 extends prod ;
`uvm_component_utils(prod1)


 

 function new(string name="",uvm_component parent);
	 super.new(name,parent);
	 endfunction
	 
 
 pkt p;
 uvm_blocking_put_port #(pkt) put_port;
 
 function void build_phase(uvm_phase phase);
   put_port=new("put_port",this);
   endfunction
   
   
   task run_phase(uvm_phase phase);
     
     repeat(3)
     begin
     p=pkt::type_id::create("p");
     assert(p.randomize()with {p.a>10;p.b==12;});
    p.display("prod1");
    
    
     put_port.put(p);
     end
     
     endtask
  endclass
  
  
  
  
  
  
  
  
   class cons extends uvm_component ;
`uvm_component_utils(cons)


 

 function new(string name="",uvm_component parent);
	 super.new(name,parent);
	 endfunction
	 
 
 pkt p;
 uvm_blocking_put_imp #(pkt,cons) imp_port;
 
 function void build_phase(uvm_phase phase);
   imp_port=new("imp_port",this);
   
   p=pkt::type_id::create("p");
   
   
   
    
  
   
   endfunction
   
   task put(pkt p1);
     this.p=p1;
    p.display("cons");
   endtask
   
  endclass
  
  
  
  
  class wrapper extends uvm_component ;
`uvm_component_utils(wrapper)

cons cn;
prod pr;
prod1 qr;





 

 function new(string name="",uvm_component parent);
	 super.new(name,parent);
	 endfunction
	 
 
 pkt p;
 
 
 
 
 function void build_phase(uvm_phase phase);
   
   pr=prod::type_id::create("pr",this);
   cn=cons::type_id::create("cn",this);
   qr=prod1::type_id::create("qr",this);
   
   endfunction
   
   
   function void connect_phase(uvm_phase phase);
     pr.put_port.connect(cn.imp_port);
     endfunction
     function void end_of_elaboration_phase(uvm_phase phase);


factory.print();

endfunction

  endclass
  
  
   class test extends uvm_component ;
`uvm_component_utils(test)



wrapper r;


 

 function new(string name="",uvm_component parent);
	 super.new(name,parent);
	 endfunction
	 
 
 
 
 
 
 
 function void build_phase(uvm_phase phase);
   prod::type_id::set_type_override(prod1::get_type(),1);
  r=wrapper::type_id::create("r",this);
   
   
   endfunction
   
   
  
   
 
  endclass
  
  
       `include "uvm_macros.svh"

import uvm_pkg::*;

module top;
initial
begin
run_test(“test”);
end
endmodule

error:-

** Note: (vsim-3813) Design is being optimized due to module recompilation…

Loading sv_std.std

Loading mtiUvm.uvm_pkg

Loading work.factoryoverride_sv_unit

Loading work.top(fast)

Loading C:\questasim_10.0b\uvm-1.0p1\win32\uvm_dpi.dll

run -all

----------------------------------------------------------------

UVM-1.0p1

(C) 2007-2011 Mentor Graphics Corporation

(C) 2007-2011 Cadence Design Systems, Inc.

(C) 2006-2011 Synopsys, Inc.

----------------------------------------------------------------

UVM_INFO @ 0: reporter [RNTST] Running test test…

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ns Iteration: 16 Process: /uvm_pkg::uvm_phase::m_run_phases File: factoryoverride.sv

Fatal error in file C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/uvm_pkg.sv

HDL call sequence:

Stopped at factoryoverride.sv 173

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 579

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 2579

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 2556

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 2536

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 2536

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 1802

called from C:/questasim_10.0b/win32/…/verilog_src/uvm-1.0p1/src/base/uvm_phases.svh 2333

quit -sim

In reply to taufeeq_khan:

You are using an incredibly old version of the UVM and old tools. And it is difficult to reproduce your problem the way it is posted. Please try your example on EDAPlayground. Asking better questions on the Verification Academy Forums with EDAPlayground - Verification Horizons