Here is my full code. Each class in in separate .sv file.
// this is the DUT, It is a simple ALU -- ALU.sv
module ALU (
input wire [3:0] operation, //The ALU ports as specified
input wire[2:0] sr_operation,
input wire [7:0] oprnd_a,oprnd_b,
input wire [7:0] input_port,
input wire [7:0] port_address,
output reg [7:0] result,
output reg zero, carry,
output reg output_port, port_id);
always @*
begin
case(operation)
4'd0: begin
result= oprnd_a;
end
4'd1: begin
result = (oprnd_a & oprnd_b);
end
4'd2: begin
result = (oprnd_a | oprnd_b);
end
4'd3: begin
result = (oprnd_a ^ oprnd_b); //XOR
end
4'd4: begin
result = (oprnd_a + oprnd_b);
end
4'd5: begin
result = (oprnd_a - oprnd_b);
end
4'd6: begin
result = (oprnd_a ~^ oprnd_b); //XNOR
end
4'd7: begin
result = (oprnd_a * oprnd_b); //multiplication
end
4'd8: begin
result = oprnd_b;
end
4'd9: begin
result = ~oprnd_a;
end
4'd10: begin
result = ~oprnd_b;
end
4'd11: begin //b
result = -oprnd_a;
end
4'd12: begin
result = -oprnd_b;
end
default: begin
result = 4'd0;
end
endcase
end
endmodule
// Sequence.sv -------- our sequencea
import uvm_pkg::*;
import my_pkg::*; //import our package here
`include"uvm_macros.svh"
// Our Sequence definition, **** VerificationAcadamy Basic Session 5
class my_seq extends uvm_sequence #(my_transaction);
`uvm_object_utils(my_seq)
function new(string name = "");
super.new(name);
endfunction: new
// This where we define the behavior of the sequence, **** VerificationAcadamy Basic Session 5
task body();
uvm_test_done.raise_objection(this);
repeat(10)
begin
my_transaction seqitem;
seqitem = my_transaction::type_id::create("seqitem"); //we creat a transaction
//hand shaking mechanisim, we use to comminucate to the Derivver **** VerificationAcadamy Basic Session 5
start_item(seqitem); // indicate to Driver that we have a transction to go
assert(seqitem.randomize()); // randomize
finish_item(seqitem); // sends the transaction to the Deriver, **** VerificationAcadamy Basic Session 5
end
uvm_test_done.drop_objection(this);
endtask: body
endclass: my_seq
// Transaction.sv ---- the transaction class
import uvm_pkg::*;
import my_pkg::*; //import our package here
`include"uvm_macros.svh"
class my_transaction extends uvm_sequence_item; //Transaction extends from UVM_item *** VerificationAcademy Basic Session 5
`uvm_object_utils(my_transaction)
function new (string name = "");
super.new(name);
endfunction: new
//Data field, randam data generation
rand logic[7:0] oprnd_a;
rand logic[7:0] oprnd_b;
rand logic[3:0] operation;
endclass: my_transaction
// Env.sv ----- the environmenta
import uvm_pkg::*;
import my_pkg::*; //import our package here
`include "uvm_macros.svh"
class my_env extends uvm_env; // Setting up the Environment
typedef uvm_sequencer #(my_transaction) my_sequencer; // we use base sequencer, **** VerificationAcademy Basic Session 5
`uvm_component_utils(my_env)
Driver Driver_h;
my_sequencer sequencer_h;
my_seq seq;
function new(string name, uvm_component parent = null);
super.new(name, parent);
endfunction: new
function void build_phase(uvm_phase phase);
// instantiate components (if any)
super.build_phase(phase);
Driver_h= Driver::type_id::create("Driver_h", this);
sequencer_h = my_sequencer::type_id::create("sequencer_h", this); //ex2
uvm_top.print_topology();
endfunction: build_phase
// Connect Phase
function void connect_phase(uvm_phase phase);
Driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction: connect_phase
// Run phase for the simiulation
task run_phase(uvm_phase phase);
seq = my_seq::type_id::create("seq");
phase.raise_objection(this);
seq.start(sequencer_h);
phase.drop_objection(this);
endtask: run_phase
function void end_of_elaboration_phase(uvm_phase phase);
uvm_top.print_topology();
endfunction
endclass: my_env
// Interface.sv ---- the interface
// Interface decleration for "Excersice 1" - it will include necessry singlas to communicate with the DUT
interface Exc1_if();
logic [3:0] operation;
logic [2:0] sr_operation;
logic [7:0] oprnd_a, oprnd_b;
logic [7:0] input_port, port_address;
logic output_port, port_id;
logic [7:0] result;
logic zero, carry;
endinterface: Exc1_if
// Pakage to include important UVM stuff
package my_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "Transaction.sv"
`include "Sequence.sv"
`include "Config.sv"
`include "Driver.sv"
`include "Env.sv"
`include "Test.sv"
endpackage: my_pkg
// Top.sv -- the top madule
module top;
import uvm_pkg::*;
import my_pkg::*; //import our package here
Exc1_if Exc1_if1 ();
my_env env_h;
ALU dut ( .operation(Exc1_if1.operation), // The connections are made to the Interface and the DUT, using the interface object and the pins of the DUT.
.sr_operation(Exc1_if1.sr_operation),
.oprnd_a(Exc1_if1.oprnd_a),
.oprnd_b(Exc1_if1.oprnd_b),
.input_port(Exc1_if1.input_port),
.port_address(Exc1_if1.port_address),
.result(Exc1_if1.result),
.carry(Exc1_if1.carry),
.zero(Exc1_if1.zero),
.output_port(Exc1_if1.output_port),
.port_id(Exc1_if1.port_id));
initial
begin
env_h = new("env_h");
uvm_config_db # (virtual Exc1_if)::set(null, "*", "top_pif", Exc1_if1);
run_test("my_test1"); // to execute the task,-- in case we have more than 1 test, we can specify wich test would be run *** VerificationAcademy session 6 video
end // in case we don't want to put the name hare, we can use "run_test();" . but in command line
endmodule: top // we can use "Vsim +UVM_TESTNAME=my_test1", to indicate the test name *** VerificationAcademy session 6 video ****