I am getting the following error while running the code.
** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 1194077892 ps Iteration: 13 Process: /chip_sim_pkg::pause_checker::t_clk_lf/#FORK#377(CLOCK1)_7feff644211 File: /eda/dm/home/skotareddy/jhr3021/v1a/digital/chip/verif/pkg/chip_sim_pkg.sv
# Fatal error in NamedBeginStat chip_sim_pkg/pause_checker::t_clk_lf/CLOCK1 at /eda/dm/home/skotareddy/jhr3021/v1a/digital/chip/verif/env/checker/pause_checker.sv line 378
#
# HDL call sequence:
# Stopped at /eda/dm/home/skotareddy/jhr3021/v1a/digital/chip/verif/env/checker/pause_checker.sv 378 NamedBeginStat chip_sim_pkg/pause_checker::t_clk_lf/CLOCK1
`ifndef PAUSE_CHECKER_SV
`define PAUSE_CHECKER_SV
class pause_checker extends uvm_monitor;
`uvm_component_utils(pause_checker)
/********* variables ***********/
logic [7:0] count;
bit clk_lf_active;
bit clk_hf_active;
/***************** declaring uvm event global pool ***********************/
uvm_event_pool verif_event_pool;
chip_cfg chip_config;
uvm_event pwrup_dig_rdy_event;
/************************************************************************/
uvm_event pause_event;
uvm_event unpause_event;
uvm_event unpause_check_event;
uvm_event pause_checker_disable;
/************************************************************************/
virtual chip_interface chip_vif;
virtual pause_if pause_vif;
function new(string name = "pause_checker",uvm_component parent);
super.new(name,parent);
endfunction:new
virtual function void build_phase(uvm_phase phase);
`uvm_info("build_phase", "pause_checker build process Starting...",UVM_LOW)
super.build_phase(phase);
chip_config = chip_cfg::type_id::create("chip_config");
if(!uvm_config_db#(virtual chip_interface)::get( .cntxt(this), .inst_name(""),.field_name("chip_vif"),.value(chip_vif)))
`uvm_fatal("Global Monitor", " chip_vif not set properly")
if(!uvm_config_db#(virtual pause_if)::get( .cntxt(this), .inst_name(""),.field_name("pause_vif"),.value(pause_vif)))
`uvm_fatal("Global Monitor", " nirq_vif not set properly")
endfunction : build_phase
virtual task run_phase(uvm_phase phase);
verif_event_pool=uvm_event_pool::get_global_pool();
pwrup_dig_rdy_event = verif_event_pool.get("resetirq");
pause_event = verif_event_pool.get("pause");
pause_event =verif_event_pool.get("pause");
unpause_event =verif_event_pool.get("unpause");
unpause_check_event=verif_event_pool.get("unpause_check");
pwrup_dig_rdy_event.wait_trigger();
if (chip_vif.nirqpol_spy == 1) begin
forever begin
t_clk_lf();
t_clk_hf();
fork
/**********************************************************************************************************************
Following block of code triggers pause event based pasueirqen and pauseirqfunc spy signals
**********************************************************************************************************************/
begin
@(negedge chip_vif.nirq_spy) begin
if(chip_vif.pauseirqen_spy == 1'b1 && chip_vif.pauseirqfunc_spy ==1'b1) begin
pause_event.trigger();
`uvm_info(get_type_name(),"PAUSEIRQEN SET AND PAUSEIRQFUNC SET ,CHIP PAUSED", UVM_LOW)
end
else if(chip_vif.pauseirqen_spy == 1'b1 && chip_vif.pauseirqfunc_spy ==1'b0) begin
pause_event.trigger();
`uvm_info(get_type_name(),"PAUSEIRQEN SET AND PAUSEIRQFUNC NOT SET ,CHIP PAUSED", UVM_LOW)
end
end
end
/**********************************************************************************************************************
Following block of code triggers unpause event based pasueirqen and pauseirqfunc spy signals
**********************************************************************************************************************/
begin
@(posedge chip_vif.nirq_spy)begin
if(chip_vif.pauseirqen_spy == 1'b1 && chip_vif.pauseirqfunc_spy ==1'b1) begin
unpause_event.trigger();
`uvm_info(get_type_name(),"PAUSEIRQEN SET AND PAUSEIRQFUNC SET ,CHIP UNPAUSED", UVM_LOW)
@(negedge chip_vif.nirq_spy);
end
else if(chip_vif.pauseirqen_spy == 1'b1 && chip_vif.pauseirqfunc_spy ==1'b0) begin
unpause_event.trigger();
`uvm_info(get_type_name(),"PAUSEIRQEN SET AND PAUSEIRQFUNC NOT SET ,CHIP UNPAUSED", UVM_LOW)
@(negedge chip_vif.nirq_spy);
end
end
end
/**********************************************************************************************************************
Following block of code checks ctrl_pause_act spy signal based on edge of the nirq spy signal (pause check)
**********************************************************************************************************************/
begin
@(negedge chip_vif.nirq_spy)begin
pause_event.wait_trigger();
if(chip_vif.pause_act_spy == 1'b1) begin
`uvm_info(get_type_name(),"chip has gone into PAUSE mode", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to PASUE mode")
end
end
end
/**********************************************************************************************************************
Following block of code checks ctrl_pause_act spy signal based on edge of the nirq spy signal (unpause check)
**********************************************************************************************************************/
begin
@(posedge chip_vif.nirq_spy)begin
unpause_event.wait_trigger();
if(chip_vif.pause_act_spy == 1'b0) begin
`uvm_info(get_type_name(),"chip has gone into UNPAUSE mode", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to UNPASUE mode")
end
end
end
/**********************************************************************************************************************
Following block of code checks for clk_hf and clk_hf after certian amount of time to check state of the chip
**********************************************************************************************************************/
begin
@(negedge chip_vif.nirq_spy)begin
pause_event.wait_trigger();
if(clk_lf_active == 1'b0 && clk_hf_active == 1'b0) begin
`uvm_info(get_type_name(),"chip has gone into PAUSE mode, PAUSEIRQEN = 1, PAUSEIRQFUNC = 0", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to PASUE mode")
end
end
end
/**********************************************************************************************************************
Following block of code checks for clk_hf and clk_hf after certian amount of time to check state of the chip
**********************************************************************************************************************/
begin
@(posedge chip_vif.nirq_spy)begin
unpause_event.wait_trigger();
if(clk_lf_active == 1'b1 && clk_hf_active == 1'b1) begin
`uvm_info(get_type_name(),"chip has gone into UNPAUSE mode, PAUSEIRQEN = 1, PAUSEIRQFUNC = 0", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to UNPASUE mode")
end
end
end
/**********************************************************************************************************************
Following block of code checks for clk_hf and clk_hf after certian amount of time to check state of the chip
pasueirqfunc enabled
**********************************************************************************************************************/
begin
@(negedge chip_vif.nirq_spy)begin
unpause_event.wait_trigger();
if(clk_hf_active == 1'b0 && clk_lf_active == 1'b1) begin
`uvm_info(get_type_name(),"chip has gone into PAUSE mode, PAUSEIRQEN = 1, PAUSEIRQFUNC = 1", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to PASUE mode")
end
end
end
/**********************************************************************************************************************
Following block of code checks for clk_hf and clk_hf after certian amount of time to check state of the chip after
unpause happens, pauseirqfunc enabled
**********************************************************************************************************************/
begin
@(posedge chip_vif.nirq_spy)begin
unpause_event.wait_trigger();
if(clk_hf_active == 1'b1 && clk_lf_active == 1'b1) begin
`uvm_info(get_type_name(),"chip has gone into UNPAUSE mode, PAUSEIRQEN = 1, PAUSEIRQFUNC = 0", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to UNPASUE mode")
end
end
end
/**********************************************************************************************************************
Following block of code checks for sensing is starting at next scan period slot if pauseirqfunc is enabled
**********************************************************************************************************************/
begin
@(posedge chip_vif.lptimer_exp_spy)begin
unpause_event.wait_trigger();
if(chip_vif.pause_act_spy == 1'b0) begin
`uvm_info(get_type_name(),"chip unpaused at next scan period boundary", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip unpasued before next scan period bounday ")
end
end
end
/**********************************************************************************************************************
Following block of code checks for sensing is starting at next scan period slot if pauseirqfunc is enabled
**********************************************************************************************************************/
begin
@(posedge chip_vif.lptimer_exp_spy)begin
unpause_check_event.wait_trigger();
if(chip_vif.nirq_spy == 1'b0) begin
`uvm_info(get_type_name(),"chip unpaused at next scan period boundary", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip unpasued before next scan period bounday ")
end
end
end
begin
@(posedge chip_vif.lptimer_exp_spy)begin
unpause_check_event.wait_trigger();
if(clk_hf_active == 1'b1 && clk_lf_active == 1'b1) begin
`uvm_info(get_type_name(),"chip has gone into PAUSE mode, PAUSEIRQEN = 1, PAUSEIRQFUNC = 1", UVM_LOW)
end
else begin
`uvm_error(get_type_name(),"Chip has not been set to UNPASUE mode")
end
end
end
join_any
end
end
endtask
/*********************************************************************************************************************
Following block of code helps in determinig clk_hf and clk_lf are active or inactive
--->*** frq must be changed during simulation.
**********************************************************************************************************************/
task automatic t_clk_lf();
fork
PERIOD1: begin
#36.571136us;
clk_lf_active=1'b0;
disable CLOCK1; // ADDED
end
CLOCK1: begin
@(chip_vif.lf_clk_spy);
clk_lf_active=1'b1;
disable PERIOD1;
end
join_any
// done=1; ->e;
endtask
task automatic t_clk_hf();
fork
PERIOD2: begin
#142.856ns;
clk_hf_active=1'b0;
disable CLOCK2; // ADDED
end
CLOCK2: begin
@(chip_vif.hf_clkspy);
clk_hf_active=1'b1;
disable PERIOD2;
end
join_any
// done=1; ->e;
endtask
endclass
`endif