FATAL ERROR

UVM
1

Hello all ,
i am getting one fatal error in connect phase of the driver class help me please what is mistake .

`ifndef driver
`define driver
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"trans.sv"
`include "interface.sv"
`include"a_config.sv"

class driver extends uvm_driver#(trans);
  `uvm_component_utils(driver)
  
  virtual mem_if.DR vif;
  trans data;
  agt_config acfg;
  
  extern function new(string name="driver",uvm_component parent);
  extern function void build_phase(uvm_phase phase);
  extern function void connect_phase(uvm_phase phase);
  extern task run_phase(uvm_phase phase); 
endclass
function driver::new(string name="driver",uvm_component parent); 
  super.new(name,parent);
endfunction
function void driver::build_phase(uvm_phase phase);
  super.build_phase(phase);
  if(!uvm_config_db#(agt_config)::get(this,"","agent_config",acfg))
    `uvm_fatal("FATAL_ERROR","agt_config cannot get have you set it??")
  endfunction
  function void driver::connect_phase(uvm_phase phase);
    vif=acfg.vif;
  endfunction
  task driver::run_phase(uvm_phase phase);
    forever
    begin
      seq_item_port.get_next_item(data);
      @(vif.driver_cb);
      vif.driver_cb.a_in<=data.a_in;
      vif.driver_cb.b_in<=data.b_in;
      vif.driver_cb.c_in<=data.c_in;
      seq_item_port.item_done();
    end
  endtask
  `endif

…===================ENVIRONMENT CLASS============//

`ifndef mem_environment
`define mem_environment
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"trans.sv"
`include"env_config.sv"
`include"agent.sv"
`include"a_config.sv"
`include"virtual_sequencer.sv"
`include"scoreboard.sv"

class mem_environment extends uvm_env;
  `uvm_component_utils(mem_environment)
  scoreboard sb;
  agent agt;
  agt_config acfg;
  virtual_sequencer vsqr;
  env_config ecfg;
  
  extern function new(string name="mem_environment",uvm_component parent);
  extern function void build_phase(uvm_phase phase);
  extern function void connect_phase(uvm_phase phase);
endclass

function mem_environment::new(string name="mem_environment",uvm_component parent);
  super.new(name,parent);
endfunction

function void mem_environment::build_phase(uvm_phase phase);
  super.build_phase(phase);
  
  if(!uvm_config_db#(env_config)::get(this,"","econfig",ecfg))
    `uvm_fatal("FATAL_ERROR_IN_ENVIRONMENT","env_config cannot get have you set it??")
    acfg=ecfg.acfg;
    
    if(ecfg.agent==1)
      begin
      uvm_config_db#(agt_config)::set(this,"*","agent_config",acfg);
      agt=agent::type_id::create("agt",this);
    end
    
    if(ecfg.has_v_sequencer==1)
      begin
      vsqr=virtual_sequencer::type_id::create("vsqr",this);
    end
    
    
    if(ecfg.has_scoreboard==1)
      begin
        sb=scoreboard::type_id::create("sb",this);
      end
    endfunction
    
      
    function void mem_environment::connect_phase(uvm_phase phase);
      if(ecfg.has_v_sequencer==1)
        begin
          agt.sqr=vsqr.sqr;
        end
        
        ///connect scoreboard with monitor
        
        if(ecfg.has_scoreboard==1)
          begin
            agt.mon.monport.connect(sb.fifo.analysis_export);
          end
        endfunction
        `endif

//=========================TEST CLASS ======================//

`ifndef test_base
`define test_base
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"mem_environment.sv"
`include"env_config.sv"
`include"a_config.sv"
`include"virtual_sequencer.sv"

class test_base extends uvm_test;
  `uvm_component_utils(test_base)

  agt_config acfg;
  virtual_sequencer vsqr;
  env_config ecfg;
  mem_environment envh;
  
  extern function new(string name="test_base",uvm_component parent);
  extern function void build_phase(uvm_phase phase);
  extern function mem_configure();

  extern function void end_of_elaboration_phase(uvm_phase phase);
endclass

function test_base::new(string name="test_base",uvm_component parent);

super.new(name,parent);
endfunction

function test_base::mem_configure();
  if(ecfg.agent==1)
    begin
      acfg=agt_config::type_id::create("acfg",this);
      if(!uvm_config_db#(virtual mem_if)::get(this,"","uvw",acfg.vif))
        `uvm_error(get_type_name,"virtual intf cannot get have you set it??")
        
        if(ecfg.agent_active==1)
          acfg.is_active=UVM_ACTIVE;
        else
          acfg.is_active=UVM_PASSIVE;
        end
      endfunction
        

function void test_base::build_phase(uvm_phase phase);
  super.build_phase(phase);
  ecfg=env_config::type_id::create("ecfg");
  mem_configure();
  
  acfg=ecfg.acfg;
  
  uvm_config_db#(env_config)::set(this,"*","econfig",ecfg);
  envh=mem_environment::type_id::create("envh",this);
endfunction

function void test_base::end_of_elaboration_phase(uvm_phase phase);
  super.end_of_elaboration_phase(phase);
  uvm_top.print_topology();
endfunction
`endif
2

In reply to raj@123:

Without showing the exact error message it is not easy to give you an advice. But it looks like the error is related to the virtual interface. Is it a member of the configuraion object an does it exist there?

3

In reply to chr_sue:

NOW TELL ME PLEASE

`ifndef agent
`define agent
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"driver.sv"
`include"sequencer.sv"
`include"monitor.sv"
`include"interface.sv"

class agent extends uvm_agent;
  `uvm_component_utils(agent)
  driver dr;
  sequencer sqr;
  monitor mon;
  agt_config acfg;
  
  extern function new(string name="agent",uvm_component parent);
  extern function void build_phase(uvm_phase phase);
  extern function void connect_phase(uvm_phase phase);
endclass
function agent::new(string name="agent",uvm_component parent);
  super.new(name,parent);
endfunction
function void agent::build_phase(uvm_phase phase);
  super.build_phase(phase);
  if(!uvm_config_db#(agt_config)::get(this,"","agent_config",acfg))
    `uvm_fatal("FATAL_ERROR","agt_config cannot get have you set it??")
    mon=monitor::type_id::create("mon",this);
    if(acfg.is_active==UVM_ACTIVE)   //*************LINE NO 29*****************//
      begin
        dr=driver::type_id::create("dr",this);
        sqr=sequencer::type_id::create("sqr",this);
      end
    endfunction
    
    function void agent::connect_phase(uvm_phase phase);
      if(acfg.is_active==UVM_ACTIVE)
        begin
          dr.seq_item_port.connect(sqr.seq_item_export);
        end
      endfunction
      `endif


//=======================agt config============================//
`ifndef agt_config
`define agt_config
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"trans.sv"
`include "interface.sv"
class agt_config extends uvm_object;
  `uvm_object_utils(agt_config)
  
  virtual mem_if vif;
  
  uvm_active_passive_enum is_active=UVM_ACTIVE;
  
  extern function new(string name="agt_config");
endclass
function agt_config::new(string name="agt_config");

  super.new(name);
endfunction
`endif
//=======================env config =====================//
`ifndef env_config
`define env_config
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"a_config.sv"
`include"interface.sv"

class env_config extends uvm_object;
  `uvm_object_utils(env_config)
  
  agt_config acfg;
  bit agent=1;
  bit agent_active=1;
  bit has_scoreboard=1;
  bit has_v_sequencer=1;
  virtual mem_if vif;
  
  
  extern function new(string name="env_aconfig");
endclass
function env_config::new(string name="env_aconfig");
super.new(name);
endfunction
`endif

//===================ERROR MESSAGE ===========================
 UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test_base...
# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ns  Iteration: 8  Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#1847_4f60f009 File: C:/questasim64_10.4e/win64/../verilog_src/uvm-1.1d/src/base/uvm_common_phases.svh
# Fatal error in Function top_sv_unit/agent::build_phase at agent.sv line 29
# 
# HDL call sequence:
# Stopped at agent.sv 29 Function top_sv_unit/agent::build_phase
4

In reply to raj@123:

Your code retrieved “agent_config” from uvm_config_db, but the value it retrieved was set to null. You need to trace back why that value was set to null.

5

In reply to dave_59:
set of agent config is correct I think .

if(ecfg.agent==1)
      begin
      uvm_config_db#(agt_config)::set(this,"*","agent_config",acfg);
      agt=agent::type_id::create("agt",this);
    end

not getting your point how to debug it means what we need to correct

6

In reply to raj@123:

Your problem is here

if (acfg.is_active==UVM_ACTIVE)

Looking to your code I see you are assigning data members to acfg. But there is no set to the configuration db. You have only a get in the agent.

7

In reply to chr_sue:

acfg(agent config) we set into the environment class and get into agent than what is issue plese let me know .

8

In reply to raj@123:

OK, I see.
In your test youa re doing:

function void test_base::build_phase(uvm_phase phase);
  super.build_phase(phase);
  ecfg=env_config::type_id::create("ecfg");
  mem_configure();
 
  acfg=ecfg.acfg;
 
  uvm_config_db#(env_config)::set(this,"*","econfig",ecfg);
  envh=mem_environment::type_id::create("envh",this);
endfunction

mem_configure assigns values to acfg

        if(ecfg.agent_active==1)
          acfg.is_active=UVM_ACTIVE;
        else
          acfg.is_active=UVM_PASSIVE;
        end

But afterwards you are overwriting these values when doing

acfg=ecfg.acfg;

Should it be

ecfg.acfg = acfg;
9

In reply to chr_sue:

Now its fine but seq not starting at test class throughing FATAL ERROR tell me why sequencer not passing.

`ifndef test_base
`define test_base
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"mem_environment.sv"
`include"env_config.sv"
`include"a_config.sv"
`include"virtual_sequencer.sv"
`include"sequence.sv"
//`include"sequencer.sv"

class test_base extends uvm_test;
  `uvm_component_utils(test_base)

  agt_config acfg;
  virtual_sequencer vsqr;
  env_config ecfg;
  mem_environment envh;
m_sequence seq;
sequencer sqr;
  
  extern function new(string name="test_base",uvm_component parent);
  extern function void build_phase(uvm_phase phase);
  extern function mem_configure();
extern task run_phase(uvm_phase phase);


  extern function void end_of_elaboration_phase(uvm_phase phase);
endclass

function test_base::new(string name="test_base",uvm_component parent);

super.new(name,parent);
endfunction

function test_base::mem_configure();
  if(ecfg.agent==1)
    begin
      acfg=agt_config::type_id::create("acfg",this);
      if(!uvm_config_db#(virtual mem_if)::get(this,"","uvw",acfg.vif))
        `uvm_error(get_type_name,"virtual intf cannot get have you set it??")
        
        if(ecfg.agent_active==1)
          acfg.is_active=UVM_ACTIVE;
        else
          acfg.is_active=UVM_PASSIVE;
        end
      endfunction
        

function void test_base::build_phase(uvm_phase phase);
  super.build_phase(phase);
  ecfg=env_config::type_id::create("ecfg");
  mem_configure();
  
  ecfg.acfg=acfg;
  
  uvm_config_db#(env_config)::set(this,"*","econfig",ecfg);
  envh=mem_environment::type_id::create("envh",this);
endfunction

function void test_base::end_of_elaboration_phase(uvm_phase phase);
  super.end_of_elaboration_phase(phase);
  uvm_top.print_topology();
endfunction

task test_base::run_phase(uvm_phase phase);
phase.raise_objection(this);
seq=m_sequence::type_id::create("seq");
seq.start(envh.agt.sqr);
#10;//set_drain_time
phase.drop_objection(this);
endtask

`endif

//===========FATAL ERROR=======================//
UVM_FATAL @ 0: reporter@@seq [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in seq

10

In reply to raj@123:

Looks like your sequencer is not parameterized with the corresponding seq_item.
You are having in your environment a virtual sequencer, but you do not use it.
Please, cleanup your code.

11

In reply to chr_sue:

sequences and sequencers and virtual sequence and virtual_sequencer , env , test

`ifndef w_sequence
`define w_sequence
import uvm_pkg::*;
`include"w_trans.sv"
`include"uvm_macros.svh"

class w_sequence extends uvm_sequence#(w_trans);
`uvm_object_utils(w_sequence)

extern function new(string name="w_sequence");
extern task body();
endclass


function w_sequence::new(string name="w_sequence");
super.new(name);
endfunction 

task w_sequence::body();
//repeat(5)
begin
req = w_trans::type_id::create("req");
start_item(req);
assert(req.randomize() with {we==1; w_addr==5; data_in==56;});

finish_item(req);
end
endtask


=====================r_sequence =====================

`ifndef r_sequence
`define r_sequence
import uvm_pkg::*;
`include"r_trans.sv"
`include"uvm_macros.svh"

class r_sequence extends uvm_sequence#(r_trans);
`uvm_object_utils(r_sequence)

extern function new(string name="r_sequence");
extern task body();
endclass


function r_sequence::new(string name="r_sequence");
super.new(name);
endfunction 

task r_sequence::body();
//repeat(5)
begin
req = r_trans::type_id::create("req");
start_item(req);
assert(req.randomize() with {re==1; r_addr==5; });

finish_item(req);
end
endtask


//===================w_sequencer========================//
`ifndef w_sequencer
`define w_sequencer
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"w_trans.sv"



class w_sequencer extends uvm_sequencer#(w_trans);

`uvm_component_utils(w_sequencer)

extern function new(string name="w_sequencer" ,  uvm_component parent);
endclass

function w_sequencer::new(string name="w_sequencer",  uvm_component parent);

super.new(name,parent);
endfunction
`endif 

//================r_sequencer====================//
`ifndef w_sequencer
`define w_sequencer
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"w_trans.sv"



class w_sequencer extends uvm_sequencer#(w_trans);

`uvm_component_utils(w_sequencer)

extern function new(string name="w_sequencer" ,  uvm_component parent);
endclass

function w_sequencer::new(string name="w_sequencer",  uvm_component parent);

super.new(name,parent);
endfunction
`endif 


//======================virtual_sequence==============================//

`ifndef virtual_sequence
`define virtual_sequence

import uvm_pkg::*;
`include"uvm_macros.svh"
`include"w_sequence.sv"
`include"w_sequencer.sv"
`include"r_sequence.sv"
`include"r_sequencer.sv"
`include"virtual_sequencer.sv"


class virtual_sequence extends uvm_sequence;
`uvm_object_utils(virtual_sequence);
w_sequence wseq;
w_sequencer wsqr;
r_sequence rseq;
r_sequencer rsqr;
virtual_sequencer vsqr;
extern function new(string name="virtual_sequence");
extern task body();
endclass 
function virtual_sequence:: new(string name="virtual_sequence");
super.new(name);
endfunction 

task virtual_sequence::body();
if(!$cast(vsqr,m_sequencer))
begin
    `uvm_error(get_full_name, "casting failed");
end 
wsqr = vsqr.wsqr;
rsqr = vsqr.rsqr;

wseq=w_sequence::type_id::create("wseq");
rseq=r_sequence::type_id::create("rseq");
repeat(5)
begin
wseq.start(wsqr);
rseq.start(rsqr);
end 
endtask
`endif 


//==================virtual_sequencer====================//


`ifndef  virtual_sequencer
`define virtual_sequencer
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"w_sequencer.sv"
`include"r_sequencer.sv"

class virtual_sequencer extends uvm_sequencer;

`uvm_component_utils(virtual_sequencer)
w_sequencer wsqr;
r_sequencer rsqr;

extern function new(string name="virtual_sequencer", uvm_component parent);
endclass
function virtual_sequencer::new(string name="virtual_sequencer" , uvm_component parent);
super.new(name,parent);
endfunction
`endif 


//=================ENVIRONMENT=====================//
`ifndef mem_environment
`define mem_environment
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"scoreboard.sv"
`include"w_agent.sv"
`include"r_agent.sv"
`include"virtual_sequencer.sv"
`include"w_config.sv"
`include"r_config.sv"
`include"env_config.sv"


class mem_environment extends uvm_env;
`uvm_component_utils(mem_environment)
scoreboard sb;
w_agent wagt;
r_agent ragt;
w_config wcfg;
r_config rcfg;
virtual_sequencer vsqr;
env_config ecfg;


extern function new(string name="mem_environment", uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);

endclass

function mem_environment::new(string name="mem_environment" , uvm_component parent);
super.new(name,parent);
endfunction 



function void mem_environment::build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(env_config)::get(this, ""  , "e_config" , ecfg))
`uvm_fatal("FATAL_ERROR IN ENVIRONMENT"  , "can't get env_config have you set it??")


// configuration assignment 
wcfg =ecfg.wcfg;
rcfg = ecfg.rcfg;


//==========WRITE PART=============//
if(ecfg.w_agent==1)
begin
uvm_config_db#(w_config)::set(this, "*", "vikash" , wcfg);

wagt =w_agent::type_id::create("wagt",this);
end 

//==========READ PART=============//
if(ecfg.r_agent==1)
begin
uvm_config_db#(r_config)::set(this, "*", "shubham" , rcfg);

ragt =r_agent::type_id::create("ragt",this);
end 




if(ecfg.has_v_sequencer==1)
begin
vsqr = virtual_sequencer::type_id::create("vsqr",this);
end 



if(ecfg.has_scoreboard==1)
begin
      sb=scoreboard::type_id::create("sb",this);
end 


endfunction


//============ connect pahase======================//

function void mem_environment::connect_phase(uvm_phase phase);
if(ecfg.has_v_sequencer==1)
fork
      if(ecfg.w_agent==1)
         begin
                  wagt.wsqr = vsqr.wsqr;
         end


if(ecfg.r_agent==1)
         begin
                  ragt.rsqr = vsqr.rsqr;
         end



join




//========connect monitors with scoreboard================//
if(ecfg.has_scoreboard==1)

begin
      wagt.wmon.wmonport.connect(sb.wfifo.analysis_export);
    
end
      

endfunction
`endif 



//=========================TEST===============================//

`ifndef test_base
`define test_base
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"mem_environment.sv"

`include"virtual_sequencer.sv"
`include"w_config.sv"
`include"r_config.sv"
`include"env_config.sv"
`include"virtual_sequence.sv"

class test_base extends uvm_test;
`uvm_component_utils(test_base)

w_config wcfg;
r_config rcfg;
virtual_sequencer vsqr;
env_config ecfg;
mem_environment envh;
virtual_sequence vseq;

extern function new(string name="test_base" , uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function mem_configure();

extern function void end_of_elaboration_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass

function  test_base::new(string name="test_base" , uvm_component parent);
super.new(name,parent);
endfunction 

//===============configuration whole testbench/////

function test_base::mem_configure();

//===============WRITE_PART  
if(ecfg.w_agent==1)
begin
wcfg = w_config::type_id::create("wcfg");
if(!uvm_config_db#(virtual mem_if)::get(this, "" , "truechip", wcfg.vif))
`uvm_error(get_type_name, "virtual intf can'y get have you set it??")

if(ecfg.wactive==1)
wcfg.is_active=UVM_ACTIVE;
else
wcfg.is_active=UVM_PASSIVE;

end 


//==============READ PART===================//

if(ecfg.r_agent==1)
begin
     rcfg = r_config::type_id::create("rcfg");
     if(!uvm_config_db#(virtual mem_if)::get(this, "" , "futurewiz", rcfg.vif))
    `uvm_error(get_type_name, "virtual intf can'y get have you set it??")
if(ecfg.ractive==1)
rcfg.is_active=UVM_ACTIVE;
else
rcfg.is_active=UVM_PASSIVE;

end 

endfunction 



//==============build_phase===================//

function void test_base::build_phase(uvm_phase phase);
super.build_phase(phase);
ecfg = env_config::type_id::create("ecfg");
mem_configure();

//wcfg = ecfg.wcfg;
//rcfg= ecfg.rcfg;

ecfg.wcfg=wcfg;
ecfg.rcfg=rcfg;
uvm_config_db#(env_config)::set(this, "*", "e_config", ecfg);
envh= mem_environment::type_id::create("mem_environment",this);
endfunction 


function void  test_base::end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
uvm_top.print_topology();

endfunction 

task test_base::run_phase(uvm_phase phase);
phase.raise_objection(this);

vseq=virtual_sequence::type_id::create("vseq");
vseq.start(envh.vsqr);

#20; // set drain time
phase.drop_objection(this);

endtask

`endif

//==========================FATAL_ERROR==========================//
UVM_FATAL @ 0: reporter@@wseq [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in wseq

— UVM Report Summary —

** Report counts by severity

UVM_INFO : 4

UVM_WARNING : 3

UVM_ERROR : 0

UVM_FATAL : 1

** Report counts by id

[Questa UVM] 2

[RNTST] 1

[SEQ] 1

[TPRGED] 3

[UVMTOP] 1

** Note: $finish : C:/questasim_10.4e/win32/…/verilog_src/uvm-1.1d/src/base/uvm_report_object.svh(292)

Time: 0 ns Iteration: 54 Region: /uvm_pkg::uvm_sequence_base::start

12

In reply to raj@123:

I believe your problem is in the virtual sequence:

....
wsqr = vsqr.wsqr;
rsqr = vsqr.rsqr;
...

You are constructing the virtual sequencer, but you do not construct inside the virtual sequencer the references to the agent sequencers.
It should be

....
vsqr.wsqr = wsqr;
vsqr.rsqr = rsqr;
...
13

In reply to chr_sue:

I did change according to you than also getting same error .


`ifndef virtual_sequence
`define virtual_sequence

import uvm_pkg::*;
`include"uvm_macros.svh"
`include"w_sequence.sv"
`include"w_sequencer.sv"
`include"r_sequence.sv"
`include"r_sequencer.sv"
`include"virtual_sequencer.sv"


class virtual_sequence extends uvm_sequence;
`uvm_object_utils(virtual_sequence);
w_sequence wseq;
w_sequencer wsqr;
r_sequence rseq;
r_sequencer rsqr;
virtual_sequencer vsqr;
extern function new(string name="virtual_sequence");
extern task body();
endclass 
function virtual_sequence:: new(string name="virtual_sequence");
super.new(name);
endfunction 

task virtual_sequence::body();
if(!$cast(vsqr,m_sequencer))
begin
    `uvm_error(get_full_name, "casting failed");
end 
//wsqr = vsqr.wsqr;
//rsqr = vsqr.rsqr;
vsqr.wsqr=wsqr;
vsqr.rsqr=rsqr;
wseq=w_sequence::type_id::create("wseq");
rseq=r_sequence::type_id::create("rseq");
repeat(5)
begin
wseq.start(vsqr.wsqr);
rseq.start(vsqr.rsqr);
end 
endtask
`endif

//======================WRTITE_SEQUENCER CLASS======= here parameterized with sequence_item=================//


`ifndef w_sequencer
`define w_sequencer
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"w_trans.sv"

class w_sequencer extends uvm_sequencer#(w_trans);

`uvm_component_utils(w_sequencer)

extern function new(string name="w_sequencer" ,  uvm_component parent);
endclass

function w_sequencer::new(string name="w_sequencer",  uvm_component parent);

super.new(name,parent);
endfunction
`endif

/=============================WSEQUENCE CLASS================================//

`ifndef w_sequence
`define w_sequence
import uvm_pkg::*;
`include"w_trans.sv"
`include"uvm_macros.svh"

class w_sequence extends uvm_sequence#(w_trans);
`uvm_object_utils(w_sequence)

extern function new(string name="w_sequence");
extern task body();
endclass


function w_sequence::new(string name="w_sequence");
super.new(name);
endfunction 

task w_sequence::body();
//repeat(5)
begin
req = w_trans::type_id::create("req");
start_item(req);
assert(req.randomize() with {we==1; w_addr==5; data_in==56;});

finish_item(req);
end
endtask

//==============================ERROR=============================//
UVM_FATAL @ 0: reporter@@wseq [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in wseq

14

In reply to raj@123:

hello chr_sue ,
I have shared whole code at your mantion email id please let me know what is the issue why sequence not starting .

15

In reply to raj@123:

I have sent the code to your email account last Sunday.
Your problem was in the virtual sequence:

wsqr = vsqr.wsqr;
rsqr = vsqr.rsqr;
//vsqr.wsqr=wsqr;
//vsqr.rsqr=rsqr;

Another weakness was in the build_phase of base_test. It should be
envh= mem_environment::type_id::create(“envh”,this);

16

In reply to chr_sue:

i didnt get ,
shubham19960720@gmail.com

please send me on this .

17

In reply to raj@123:

i did above two change than also sequence not getting sequencer .

18

In reply to chr_sue:

In reply to raj@123:
I have sent the code to your email account last Sunday.
Your problem was in the virtual sequence:
wsqr = vsqr.wsqr;
rsqr = vsqr.rsqr;
//vsqr.wsqr=wsqr;
//vsqr.rsqr=rsqr;
Another weakness was in the build_phase of base_test. It should be
envh= mem_environment::type_id::create(“envh”,this);

`ifndef virtual_sequence
`define virtual_sequence

import uvm_pkg::*;
`include"uvm_macros.svh"

`include"w_sequence.sv"
`include"r_sequence.sv"
`include"w_sequencer.sv"
`include"r_sequencer.sv"
`include"virtual_sequencer.sv"


class virtual_sequence extends uvm_sequence;

`uvm_object_utils(virtual_sequence)

w_sequence wseq;
w_sequencer wsqr;
r_sequence rseq;
r_sequencer rsqr;

virtual_sequencer vsqr;

extern function new(string name="virtual_sequence");
extern task body();
endclass


function virtual_sequence::new(string name="virtual_sequence");
super.new(name);
endfunction


////-----------------------BODY------

task virtual_sequence::body();

if(!$cast(vsqr,m_sequencer))
begin

`uvm_error(get_full_name,"CASTING OF VIRTUAL SEQUENCER FAILED");

end


wsqr=vsqr.wsqr;
rsqr=vsqr.rsqr;

endtask



/////////////////////////////////////////////////////////////TESTCASE PURPOSE



class virtual_sequence1 extends virtual_sequence;

`uvm_object_utils(virtual_sequence1)

w_sequence1 wseq1;
r_sequence1 rseq1;


extern function new(string name="virtual_sequence1");
extern task body();
endclass


function virtual_sequence1::new(string name="virtual_sequence1");
super.new(name);
endfunction


/////////////------------BODY METHOD

task virtual_sequence1::body();
super.body();

wseq1=w_sequence1::type_id::create("wseq1");
rseq1=r_sequence1::type_id::create("rseq1");


repeat(5)
begin
wseq1.start(wsqr);
rseq1.start(rsqr);
end
endtask
`endif 




//====================== test class==========================//
`ifndef test_base
`define test
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"env_config.sv"
`include"mem_environment.sv"
`include"w_config.sv"
`include"r_config.sv"
`include"virtual_sequence.sv"
`include"virtual_sequencer.sv"


class test_base extends uvm_test;
`uvm_component_utils(test_base)

mem_environment envh;

virtual_sequence vseq;
virtual_sequencer vsqr;
w_config wcfg;
r_config rcfg;

env_config ecfg;

extern function new(string name="test_base",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void mem_configure();
extern function void end_of_elaboration_phase(uvm_phase phase);



endclass



function test_base::new(string name="test_base",uvm_component parent);
super.new(name,parent);
endfunction


function void test_base::mem_configure();

//------------------------ WRITE PART
if(ecfg.w_agent==1)
begin
      wcfg=w_config::type_id::create("wcfg");
     if(!uvm_config_db#(virtual mem_if)::get(this,"","truechip",wcfg.vif))
     `uvm_error(get_type_name(),"can't get have you set it????")
     
     if (ecfg.wactive)
         wcfg.is_active=UVM_ACTIVE;
     else
         wcfg.is_active=UVM_PASSIVE;
end


//------------------------------------READ PART

if(ecfg.r_agent==1)
begin
      rcfg=r_config::type_id::create("rcfg");
     if(!uvm_config_db#(virtual mem_if)::get(this,"","futurewiz",rcfg.vif))
     `uvm_error(get_type_name(),"can't get have you set it????")
     
     begin
     if (ecfg.ractive)
         rcfg.is_active=UVM_ACTIVE;
     else
         rcfg.is_active=UVM_PASSIVE;
     end
end

endfunction


/////////////////BUILD_PHASE

function void test_base:: build_phase(uvm_phase phase);
super.build_phase(phase);

ecfg=env_config::type_id::create("ecfg");

mem_configure();

ecfg.rcfg = rcfg;
ecfg.wcfg = wcfg;
uvm_config_db#(env_config)::set(this,"*","e_config",ecfg);


envh= mem_environment::type_id::create("envh",this);
endfunction

//////---------- TOPOLOGY PRINTING PURPOSE-------------------------

function void test_base::end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);

uvm_top.print_topology();
endfunction




/////////////////////////TEST-CASE PURPOSE

class test1 extends test_base;
`uvm_component_utils(test1)


virtual_sequence1 vseq1;

extern function new(string name="test1",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);

endclass

function test1::new(string name="test1",uvm_component parent);
super.new(name,parent);
endfunction


function void test1::build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction


//-------------RUN_PHASE------------------------------------------

task test1::run_phase(uvm_phase phase);

phase.raise_objection(this);

vseq1=virtual_sequence1::type_id::create("vseq1");
vseq1.start(envh.vsqr);

#100;//// SET DRAIN TIME
phase.drop_objection(this);

endtask

`endif

//==================ERROR===================//

UVM_FATAL @ 0: reporter@@wseq1 [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in wseq1

19

In reply to raj@123:

You’ll find the whole code here
private link removed

20

In reply to chr_sue:

In reply to raj@123:
You’ll find the whole code here
private link removed

Your problem was in the virtual sequence:

wsqr = vsqr.wsqr;
rsqr = vsqr.rsqr;
//vsqr.wsqr=wsqr;
//vsqr.rsqr=rsqr;

Another weakness was in the build_phase of base_test. It should be
envh= mem_environment::type_id::create(“envh”,this);

apart from these two error is there any other issue .
why because i did same thing in test and virtual sequence class than also getrrting same fata error .

UVM_FATAL @ 0: reporter@@wseq1 [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in wseq1