Factor override does not occur. Need to know why? pls see code below

class mytran extends uvm_sequence_item;

  `uvm_object_utils(mytran)  //register in the factory

  string msg ;
  rand int a ;
  rand int b ;
  int sum ;

  constraint a_c { a inside {[0:10]};}
  constraint b_c { b inside {[0:10]};}

  function new (string name = "mytran");
    super.new(name) ;

  endfunction

  virtual function void print () ;
    `uvm_info("in item)(in parent)", get_full_name(), UVM_LOW);
    `uvm_info("in item)(in parent: type name)", get_type_name(), UVM_LOW);
  endfunction

endclass


class mytran_new extends mytran;

  `uvm_object_utils(mytran_new)  //register in the factory

  rand int c ;
  rand int d ;


  function new (string name = "mytran_new");
    super.new(name) ;
  endfunction

  function void print () ;
    `uvm_info("in item)(in parent)", get_full_name(), UVM_LOW);
  endfunction

endclass


class adder_model_test extends uvm_test;

  `uvm_component_utils(adder_model_test)

  adder_model_env env;
  mytran_sequence  seq;

  function new(string name = "adder_model_test",uvm_component parent=null);
    super.new(name,parent);
  endfunction : new

  virtual function void build_phase(uvm_phase phase);

    super.build_phase(phase);
    //factory code below this line:
    set_type_override_by_type(mytran::get_type(), mytran_new::get_type(), 1'b1) ;
     

    env = adder_model_env::type_id::create("env", this);
    seq = mytran_sequence::type_id::create("seq", this);

  endfunction : build_phase

  task run_phase(uvm_phase phase);
          phase.raise_objection(this);
    `uvm_info($sformatf("%0d", $time), "connect the sequence to the sequencer before", UVM_LOW)
    `uvm_info(get_type_name(), "connect the sequence to the sequencer before", UVM_LOW)
          seq.p_sequencer = env.adder_agnt.sequencer ;
    if(seq.p_sequencer == null) begin
      `uvm_fatal("The sequencer is null", "") ;
    end
          seq.start(env.adder_agnt.sequencer);

    `uvm_info(get_full_name(), "connect the sequence to the sequencer later", UVM_LOW)
          phase.drop_objection(this);
  endtask : run_phase

endclass : adder_model_test


In reply to samerh:

Please use code tags making your code easier to read. I have added them for you.

You never showed creation of a mytran class to be overridden, but the call to set_type_override_by_type() would only override the mytran class created in the adder_model_test component. You probably want to do a global type override.

    uvm_factory::get().set_type_override_by_type(mytran::get_type(), mytran_new::get_type(), 1'b1) ;


In reply to dave_59:

I tried your fix and it did not override. Here is the reset of the code:

class mytran extends uvm_sequence_item;

  `uvm_object_utils(mytran)  //register in the factory

  string msg ;

//class mytran # (parameter type data = int) ;

  rand int a ;
  rand int b ;
  int sum ;

  constraint a_c { a inside {[0:10]};}
  constraint b_c { b inside {[0:10]};}

  function new (string name = "mytran");
    super.new(name) ;

  endfunction

  virtual function void print () ;
    `uvm_info("in item)(in parent)", get_full_name(), UVM_LOW);
    `uvm_info("in item)(in parent: type name)", get_type_name(), UVM_LOW);
  endfunction

endclass


class mytran_new extends mytran;

  `uvm_object_utils(mytran_new)  //register in the factory

  rand int c ;
  rand int d ;


  function new (string name = "mytran_new");
    super.new(name) ;
  endfunction

  function void print () ;
    `uvm_info("in item)(in parent)", get_full_name(), UVM_LOW);
  endfunction

endclass


class adder_sequencer extends uvm_sequencer #(mytran);
  `uvm_component_utils(adder_sequencer)

  //constructor
  function new(string name, uvm_component parent);
    super.new(name,parent);
  endfunction

endclass


class mytran_sequence extends uvm_sequence #(mytran, mytran);

  `uvm_object_utils(mytran_sequence)
  //`uvm_declare_p_sequencer(adder_sequencer)
  //The above macro exeuctes this function:
  //`define uvm_declare_p_sequencer(SEQUENCER) \


  adder_sequencer  p_sequencer;
  virtual function void m_set_p_sequencer();
    super.m_set_p_sequencer();
    if( !$cast(p_sequencer, m_sequencer))
        `uvm_fatal("DCLPSQ", $sformatf("%m %s Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer", get_full_name()))
  endfunction


  // adder_sequencer ;

  rand mytran mytran0 ;
  mytran rsp ;

    function new (string name = "mytran_sequence") ;
      super.new(name);
      mytran0 = mytran::type_id::create("tran-0") ;
      rsp = new ; //already defined so there is no need for this line. 
      m_set_p_sequencer();
    endfunction




  function void pr ;

    $display("(from sequence): value of a = %d, b = %d", mytran0.a, mytran0.b) ;
    //$display("(from sequence): value of c = %d, d = %d", mytran0.c, mytran0.d) ;
    mytran0.print() ; 
  endfunction




  virtual task body ( ) ; //runtime task
    begin

    for (int i = 0 ; i < 10; i++) begin

      if(mytran0.randomize()) begin
        pr() ;
        wait_for_grant();
        send_request(mytran0);
        wait_for_item_done();
        get_response(rsp) ; //recieve a response from the sequencer
        `uvm_info("(in sequence): here is the response message", rsp.msg, UVM_LOW);
        //$display("(from sequence): value of c = %d, d = %d", mytran0.c, mytran0.d) ;
      end

    end
    end
  endtask


endclass