Expanding simulation time

Hi,

I’m running a sequence from USER_DATA_PHASE. the problem I see is that the simulation ends but there is still traffic didn’t collect to the SB from the DUT.
I’ve tried many solutions like adding delay to the end of the USER_DATA_PHASE (it expands the duration of this phase but the packets from the DUT still don’t get collected - I know it’s not a problem of the DUT).
I’ve also tried to add flush sequence and add the delay there, but still I see no change.
is anyone has an idea how to overcome this issue?

Thanks,
Moshiko

In reply to moshiko:

I see 2 options for your problem:
(1) set_drain_time(). This allows you to extend the run_phase by a fixed time.
(2) functional extension using phase_ready_to_end().

Please see the Reference Manual for more details.

In reply to moshiko:

See An Overview of UVM End-of-Test Mechanisms | Verification Gentleman Blog