Execution interrupted or reached maximum runtime

Hello,

I am trying ACE Protocol UVC UVM TB in EDA playground. Here is the link :

I am getting this error :
Execution interrupted or reached maximum runtime.
Done

I have created 3 difeerent agents-read, write and snoop and follow same for hierarchy components. I have not added any simulation timeout limit. I am not able to spot an infinite loop code. Could you help find out if there is one? If not, what else could cause this error?

Thanks,
Paresh

In reply to paresh123:

Looks like you are running in an forever loop.
In your driver’s runphase you are doing
fork
master_read_addr(ace_seq_item_read);
master_read_data(ace_seq_item_read);
master_read_resp(ace_seq_item_read);
join

I gues you want to run 1st read_addr, then read_data and last but not least read_resp.

In your fork/join this order is not guaranteed. It selects any of the enries first and then it continues withg another task.
And your driver gets only 1 seq_item.

Yes sir , I have updated my files now ,read driver is genrating all the sequences but its stuck at write driver now. I have added two events.
it displays only one sequence although logic is same now for read as well as write.
Please take a look at my file again and help me in this

In reply to paresh123:

YAou are doing things very complicated. Finally you have only 1 pinlevel interface. This requires only 1 agent and not 3. All the functionality you need you can implement in a 1 agent implementation.
I did a few modifications with respect to the body tasks of the sequences. This is how it should look like.
Currently your simulation is hanging in the read mode because it is waiting for the ready signal which does not exist See line 111 in your ace_driver_read ( wait(ace_intf.RREADY == 1’b1);)

I have define 3 agents to differentiate read ,write and snoop signals.
line 111 i have done changes now its running. I have one doubt regarding slave driver file, Can i implement slave driver in any one of the read, write or snoop

In reply to paresh123:

Again the number of pinlevel interfaces determines the number of agents And this 1!
raéad, write and snoop are functionalies to be implemented in the driver.
I do not understand your question. If you are implementing in your tesbench master functionality then the design behaves as a slave. Ther is not slave agent.

yes I want to implement master uvc.In slave driver ,i have written logic for wrap boundary and burst conditon and address calculation and stored it in queue. So can i do this part in any of these driver

In reply to paresh123:

Either your UVM testbench is the masster and the DUT is the slave or the testbench is the slave, then the DUT is the master.
I guess you want to implement a UVC whci covers the master and the slave funcionality. But both functionalities will not be active at the same time. You can configure the UVM testbench either as master or as slave.

No I’m want to implement ACE UVC for which DUT is not there. It is only generation of ACE signals which acts as master and then in future we can integrate with programmable cache memory to form ACE IP consisting master UVC and cache memory as slave