Hi,
I am trying implement RAL. I am getting following UVM_WARNING and my test is hanging.
UVM_WARNING /synopsys/vcs_mx_J-2014.12-sp3/etc/uvm/reg/uvm_reg_sequence.svh(137) @ 0: uvm_test_top.env.sagent.ssp_seqr@@s_seq [REG_XLATE_NO_SEQR] Executing RegModel translation sequence on sequencer uvm_test_top.env.sagent.ssp_seqr' does not have an upstream sequencer defined. Execution of register items available only via direct calls to 'do_rw_access'
MY code :
class spi_reg_wr_rd_ral extends my_test;
`uvm_component_utils(spi_reg_wr_rd_ral)
spi_reg_wr_rd_seq_ral s_seq;
extern function new (string name = "spi_reg_wr_rd_ral" , uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass : spi_reg_wr_rd_ral
function spi_reg_wr_rd_ral :: new (string name = "spi_reg_wr_rd_ral", uvm_component parent);
super.new(name, parent);
endfunction
function void spi_reg_wr_rd_ral :: build_phase (uvm_phase phase);
super.build_phase(phase);
`uvm_info("SPI_DUT_MSTR_TX_TEST","\n\t Entering spi_reg_wr_rd_ral build phase",UVM_LOW)
s_seq = spi_reg_wr_rd_seq_ral ::type_id::create ( .name("s_seq"), .contxt (get_full_name()));
`uvm_info("SPI_DUT_MSTR_TX_TEST","\n\t Exiting spi_reg_wr_rd_ral build phase",UVM_LOW)
endfunction
task spi_reg_wr_rd_ral :: run_phase (uvm_phase phase);
phase.raise_objection(this);
//start the sequencer
s_seq.reg_block = reg_block ;
s_seq.start(.sequencer (env.sagent.ssp_seqr));
phase.drop_objection(this);
endtask
BASE TEST - > my_test
class my_test extends uvm_test;
`uvm_component_utils(my_test)
virtual ssp_if intf1;
virtual ssp_if intf2;
ssp_env env;
ssp_env_config env_cfg;
ssp_agent_config sagent_cfg;
trick_agent_config tagent_cfg;
ssp_reg_block reg_block;
extern function new (string name = "my_test" , uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern function void start_of_simulation_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass : my_test
function my_test :: new (string name = "my_test", uvm_component parent);
super.new(name, parent);
endfunction
function void my_test :: build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("MY_TEST","\n\t Entering my_test build phase ",UVM_LOW);
reg_block = ssp_reg_block::type_id::create( "reg_block" );
reg_block.build();
env_cfg = ssp_env_config::type_id::create("env_cfg");
env_cfg.reg_block = reg_block;
sagent_cfg = ssp_agent_config::type_id::create("sagent_cfg");
tagent_cfg = trick_agent_config::type_id::create("tagent_cfg");
if(!uvm_config_db #(virtual ssp_if)::get(this,"","ssp_if",intf1))
`uvm_fatal("MY_TEST","No virtual interface set at top for trick agent")
if(!uvm_config_db #(virtual ssp_if)::get(this,"","trick_if",intf2))
`uvm_fatal("MY_TEST","No virtual interface set at top for ssp agent")
sagent_cfg.intf = intf1 ;
tagent_cfg.intf = intf2;
env_cfg.sagent_cfg = sagent_cfg;
env_cfg.tagent_cfg = tagent_cfg;
env = ssp_env::type_id::create(.name("env"),.parent(this));
uvm_config_db#(ssp_env_config)::set(this,"*","env_cfg",env_cfg);
`uvm_info("MY_TEST","\n\tExiting my_test build phase ",UVM_LOW);
endfunction : build_phase
function void my_test :: start_of_simulation_phase(uvm_phase phase);
uvm_test_done.set_drain_time(this, 600);
uvm_test_done.set_report_verbosity_level(UVM_HIGH);
endfunction : start_of_simulation_phase
