Error: (vlog-13069) E:/Questasim/examples/180121/uvm_write_txn.sv(9): near "uvm_sequence_item": syntax error, unexpected IDENTIFIER. ** Error: E:/Questasim/examples/180121/uvm_write_txn.sv(9): Error in class extension specification

UVM
,
1

Hi, I am using Questasim 10.7c, though i have included all the required UVM library files i am getting following error.

** Error: (vlog-13069) E:/Questasim/examples/180121/uvm_write_txn.sv(9): near “uvm_sequence_item”: syntax error, unexpected IDENTIFIER.
** Error: E:/Questasim/examples/180121/uvm_write_txn.sv(9): Error in class extension specification.

Below are the files i am compiling in the order pasted below
File1 & File 4 are compiling without any errors, but File 2 & File 4 i am getting the errors mentioned above. May i know how to resolve.

File 1 - tb_defs.sv

`define RAM_WIDTH 64
`define ADDRESS_SIZE 12

typedef enum bit {BAD_TXN, GOOD_TXN} addr_t;

File 2 - ram_pkg.sv

package ram_pkg;

import uvm_pkg::*;

`include "uvm_macros.svh"
`include "tb_defs.sv"
`include "uvm_wr_txn_macro.sv"

//`include "short_txn.sv"
//`include "uvm_write_txn.sv"

endpackage

File 3 - uvm_wr_txn_macro.sv

//import uvm_pkg ::*;
import ram_pkg ::*;

class write_txn extends uvm_sequence_item;

rand bit [`RAM_WIDTH-1 : 0] data;
rand bit [`ADDRESS_SIZE-1 : 0] addr;
rand bit write;

rand addr_t txn_type;
rand bit [63:0] txn_delay;

`uvm_object_utils_begin (write_txn)
`uvm_field_int (data, UVM_ALL_ON);
`uvm_field_int (addr, UVM_ALL_ON);
`uvm_field_int (write, UVM_ALL_ON);
`uvm_field_enum (addr_t, txn_type, UVM_ALL_ON);
`uvm_field_int (txn_delay, UVM_ALL_ON);
`uvm_object_utils_end


constraint a { data inside {[20:90]};
		addr inside {[0:200]};
		txn_type dist {BAD_TXN := 2, GOOD_TXN := 30};}


function new (string name = "write_txn");
super.new (name);
endfunction

function void post_randomize();

//constraint b {txn_type == BAD_TXN -> addr = 12'd6000;}

endfunction

endclass

File 4 - uvm_si_top.sv


module top;

import uvm_pkg ::*;

import ram_pkg ::*;

write_txn wr_copy_txnh, wr_clone_txnh;

write_txn write_txnh[];

int no_trans = 10;

initial

begin

	write_txnh = new[no_trans];

	for (int i = 0; i < 10; i++)
	begin
		write_txnh = write_txn :: type_id :: create ($sformatf("write_txnh[%0d]",i));
		assert (write_txnh[i].randomize());
		write_txnh[i].print(uvm_default_table_printer);	
	end

	write_txnh[3].copy(write_txnh[5]);
	
	wr_copy_txnh = write_txn :: type_id :: create (wr_copy_txnh);
	wr_copy_txnh.copy(write_txnh[3]);

	wr_copy_txnh.print (uvm_default_table_printer);

	if (write_txnh[3].compare(write_txnh[5]))
		$display("COMPARISION SUCCESSFUL");
	else
		$display("COMPARISION FAILURE");

	$cast (wr_clone_txnh, write_txnh[8].clone());
	wr_clone_txnh.print (uvm_default_tree_printer);


end


endmodule
2

In reply to vijaykumarvec:

What you say you are compiling does not make sense. File 2 `includes file 1 and 3, you would need to compile file 2 first, and not put file 1 and 3 on the command line. File 4 imports ram_pkg, which is defined by the contents of file 2, it would not compile successfully unless all of the other files compiled successfully.

3

In reply to vijaykumarvec:
What you say you are compiling does not make sense. File 2 `includes file 1 and 3, you would need to compile file 2 first, and not put file 1 and 3 on the command line. File 4 imports ram_pkg, which is defined by the contents of file 2, it would not compile successfully unless all of the other files compiled successfully.

Hi Dave, I changed the Compile order, now i am compiling in the following order
File 2
File 1
File 3
File 4
Now File 2 & 1 are compilied successfully without any error, but File 3 i am getting the same error - ** Error: (vlog-13069) E:/Questasim/examples/180121/uvm_wr_txn_macro.sv(4): near “uvm_sequence_item”: syntax error, unexpected IDENTIFIER.
** Error: E:/Questasim/examples/180121/uvm_wr_txn_macro.sv(4): Error in class extension specification.
May i know why? I guess problem is with accessing UVM Library files.

4

In reply to vijaykumarvec:

You should only compile files 2 & 4.

5

In reply to dave_59:

In reply to vijaykumarvec:
You should only compile files 2 & 4.

Thanks a lot Dave. It worked.