Error : null object access

class master_drv extends uvm_driver #(master_txn);
  `uvm_component_utils(master_drv)
 
  master_agt_config m_cfgh;
  virtual uart_inf vif;
  master_txn xtnh;
   
   
    logic   [31:0]      divisor;
    time               	clk_prd;
    real 			    clk_frq;     
    reg     [31:0]      cnt;   
   	time 				clk_rise_edge ;
    logic bclk;
  
  //////////////////new_constructor//////////////////////////////
  
  function new(string name="master_drv",uvm_component parent);
    super.new(name,parent);
  endfunction
  
  /////////////////////////////build_phase//////////////////////////////
  virtual function void buid_phase(uvm_phase phase);
    super.build_phase(phase);
  
    if(!uvm_config_db#(master_agt_config)::get(this,"","master_agt_config",m_cfgh))
    `uvm_fatal("MASTER","cannot get the master config from config_db");
     
    
   xtnh=master_txn::type_id::create("xtnh");
    
  endfunction
  
  ////////////////////////////connect_phase/////////////////////////
  
  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);
   vif=m_cfgh.vif;
  endfunction
  
  
  ////////////////////run_phase/////////////////////////////
  
  task run_phase(uvm_phase phase);
    
    @(posedge vif.g_clk)
     vif.g_rst<=0;
    
    @(posedge vif.g_clk)    
       vif.g_rst<=1;
    
   forever 
       begin
        seq_item_port.get_next_item(req);
         uart_bclk(req);       
        seq_item_port.item_done();
      end
  endtask
  
  task uart_bclk(master_txn xtnh);  
   forever
  	begin
    
      @(posedge vif.g_clk) 
    
        
      clk_rise_edge = $time; 
      $display( "time = %t ; clk_rise_edge = %t",$time, clk_rise_edge);
  
      @(posedge vif.g_clk) begin
     	 clk_prd = $time -  clk_rise_edge;    
   		 clk_frq = 1e9 / (clk_prd );
    $display( "frequency = %g ",clk_frq);    
    divisor = clk_frq / (xtnh.baud_rate);
    $display( "divisor= %d ",divisor);
  	
  end
    end  
  
    @ (posedge vif.g_clk or posedge vif.g_rst)
    begin
      if(vif.g_rst) begin
        cnt  <= 32'd0;
      	bclk <= 1'b0;
        
        
      end
      else if(cnt >= divisor) begin
        bclk <= 1'b1;
      	cnt  <= 32'd0;
      end
      else begin
        cnt <= cnt + 1'b1;
      	bclk<= 1'b0;
      end
    end
    
    
  endtask
    
    
    
    
endclass

Error-[NOA] Null object access
master_drv.sv, 38
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.

line no 38 : vif = mcfgh.vif;

even though i have constructed config am getting null object access.
may i know what is wrong with the code

In reply to ranju.ranjitha555@gmail.com:

Success when calling uvm_config_db::get() indicates that the requested type/id exists in the uvm_config_db. You can still pass a null value, which is what I’m guessing that you did when you called set(). Verify that m_cfgh is valid when you call set().