Error [NOA] Null Object Access The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it

UVM
,
1

I am getting this error during this simulation in scoreboard


//ALU_SCOREBOARD

import uvm_pkg::*;
`include "uvm_macros.svh"

class alu_scoreboard extends uvm_scoreboard;

//Factory registration
`uvm_component_utils(alu_scoreboard)

//Define analysis port

uvm_analysis_imp #(data_packet, alu_scoreboard) dp_imp;
uvm_tlm_analysis_fifo #(data_packet) inp_fifo;
uvm_tlm_analysis_fifo #(data_packet) mon_fifo;

//Create sequence item
data_packet dp;

//Construct function new
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction

//Build phase
function void build_phase(uvm_phase phase);
dp_imp = new("dp_imp", this);
dp = data_packet::type_id::create("dp", this);
endfunction: build_phase

logic [2:0] dout;
logic flag_1;

task write_fifo(data_packet dp1);
`uvm_info("input_data", "expected data prediction", UVM_LOW)
fork
if(!dp1.resetn)begin
 dout <= 0;
 flag_1 <= 0;
end
else if(dp1.inp_en) begin
 if(dp1.opcode) begin
  dout <= dp1.a + dp1.b;
  flag_1 <= 1;
 end
 else begin
  dout <= dp1.a - dp1.b;
  flag_1 <= 1;
 end
 end
else begin
 dout <= 0;
 flag_1 <= 0;
end

if(!dp.resetn) begin
 dp1.outp <= 0;
 dp1.valid_out <= 0;
end
else if (flag_1 == 1) begin
 dp1.outp <= dout;
 dp1.valid_out <= 1;
 flag_1 <= 0;
// void'(inp_fifo.try_put(dp1));
// `uvm_info("input_data", "data sent into fifo", UVM_LOW)
end
else begin
dp1.outp <= 0;
dp1.valid_out <= 0;
end
join
if (flag_1 == 1) begin
  void'(inp_fifo.try_put(dp1));
 `uvm_info("input_data", "data sent into fifo", UVM_LOW)
end
endtask: write_fifo

function void write(data_packet dp2);
`uvm_info("actal_data", "actual data", UVM_LOW)
void'(mon_fifo.try_put(dp2));
endfunction: write

//Run phase
virtual task run_phase(uvm_phase phase);
forever begin
//fork
data_packet  exp, act;
fork
 write_fifo(dp);
join
`uvm_info("scoreboard run task", "expected data", UVM_LOW)
 inp_fifo.get(exp);                                            //error is shown at this line number
`uvm_info("scoreboard run task", "actual data", UVM_LOW)
 mon_fifo.get(act);

if(act.compare(exp))
`uvm_info("scoreboard run task", "Test PASS", UVM_LOW)
else
`uvm_info("scoreboard run task", "Test FAIL", UVM_LOW)
//join
end
endtask

endclass : alu_scoreboard
2

In reply to mani20794:

You should use code tags to make your code readible.
A few remarks:
(1) Your error message should point you to a specific line of code. Please show this line.
(2) I do not understand these lines of code:

if(!dp.resetn) begin
  dp1.outp <= 0;
  dp1.valid_out <= 0;
end

Looks like dependency from the virtual interface. Commonly you do not have to consider the reset on the transaction level.
(3) A seq_item will not be constructed during the build_phase. It has to be constructed somewhere in the run_phase, because the seq_item does not belong to the testbench hierarchy.

3

In reply to mani20794:

You never create inp_fifo or mon_fifo.