Error - near "#": syntax error, unexpected '#', expecting IDENTIFIER or '='

UVM
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1

Hello, i am building a parametrizable UVC and i am getting this error in the top environment of the UVC.

This is the beginning of the environment:

class ds_env#(int PARALLEL_CORE_WIDTH=40) extends uvm_env;
`uvm_component_param_utils(ds_env#(PARALLEL_CORE_WIDTH))
//----------------------------------------------------------

// Environment Configuration Parameters
ds_config cfg; // environment configuration object

// Components of the environment
ds_agent#(PARALLEL_CORE_WIDTH) h_ds_agents;//THE ERROR IS IN THIS LINE OR IN THE NEXT IF I COMMENT THIS ONE OUT
ds_scoreboard#(PARALLEL_CORE_WIDTH) tx_scoreboards;
ds_scoreboard#(PARALLEL_CORE_WIDTH) rx_scoreboards;
ds_scoreboard#(PARALLEL_CORE_WIDTH) loopback_scoreboards;

The beginning of the ds_agent class is as follow:

class ds_agent#(int PARALLEL_CORE_WIDTH=40) extends uvm_agent;
`uvm_component_param_utils(ds_agent#(PARALLEL_CORE_WIDTH))
//----------------------------------------------------------

// Environment Configuration Parameters
ds_config cfg; // environment configuration object

// Components of the agent
ds_tx_agent#(PARALLEL_CORE_WIDTH) tx_active_agents;
ds_tx_agent#(PARALLEL_CORE_WIDTH) tx_passive_agents;
ds_rx_agent#(PARALLEL_CORE_WIDTH) rx_active_agents;
ds_rx_agent#(PARALLEL_CORE_WIDTH) rx_passive_agents;
uvm_analysis_port #(ds_seq_item#(PARALLEL_CORE_WIDTH)) h_trans_item_collected_ap[4];

And the beginning of the scoreboard is this:

class ds_scoreboard#(int PARALLEL_CORE_WIDTH=40) extends uvm_scoreboard;
`uvm_component_param_utils(ds_scoreboard#(PARALLEL_CORE_WIDTH))

uvm_analysis_imp_decl(_input_port) uvm_analysis_imp_input_port#(ds_seq_item#(PARALLEL_CORE_WIDTH),ds_scoreboard#(PARALLEL_CORE_WIDTH)) in_trans_imp; uvm_analysis_imp_decl(_output_port)
uvm_analysis_imp_output_port#(ds_seq_item#(PARALLEL_CORE_WIDTH),ds_scoreboard#(PARALLEL_CORE_WIDTH)) out_trans_imp;

When i conpile i get this error:

** Error: (vlog-13069) ** while parsing file included at …/uvm/serdes_tb_top.sv(7)
** while parsing file included at …/uvm/serdes_pkg.sv(7)
** while parsing file included at …/uvm/ds_uvc/ds_pkg.sv(14)
** at …/uvm/ds_uvc/ds_env.sv(12): near “#”: syntax error, unexpected ‘#’, expecting IDENTIFIER or ‘=’.

I have checked all the components just to see if i was missing any parameter but everything seems fine, could you please give me any suggestion??

Thank you

2

In reply to jcaballero1987:

Most likely this is because are referencing a class before its declaration. SystemVerilog requires all type identifiers to be known before any code that references it can be parsed. Often this problem can be fixed by re-ordering your class declarations. But finding a correct ordering is not always possible when you have cyclic class dependencies. For that you can use a forward typedef. That tells the compiler that an identifier is a type without fully defining it immediately— that’s just enough information for the compiler to figure out what statement you’re trying to put together.

Cyclic dependencies are something to avoid if possible. It makes separating your code into independent re-usable blocks more difficult. It seems to me you are putting most of the testbench hierarchy into your config class.

3

Thank you so much Dave, i just re-ordered my class declaration in the package and the error is gone. I am not using cyclic dependencies but i agree that can be pretty difficult to re-order in that case. Thanks a lot.