Error : formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_pkg::uvm_component' but found 'packed array' instead)

UVM
1

Hi i just tried compiling my testbench top and above mentioned error started popping up

`include "uvm_macros.svh"
import uvm_pkg::* ;
//`include "d_ff_item.sv"
//`include "sequence.sv"
//`include "driver.sv"
//`include "monitor.sv"
//`include "agent.sv"
//`include "scoreboard.sv"
//`include "d_ff_env.sv"
//`include "d_ff_test.sv"
//`include "d_ff_intf.sv"
module tb;
  logic clk;
  d_ff_intf vif(clk);
  d_ff dut(.clk(clk),.rst(vif.rst),.d(vif.d),.q(vif.q));

  initial
    clk = 1'b0;

   always begin
     forever
       #5 clk = ~clk;
   end

  initial begin
    uvm_config_db#(virtual d_ff_intf)::set("null","test","d_ff_intf",vif);
    `uvm_info("TOP","Set the interface from the top",UVM_LOW);
    run_test("d_ff_test");
    #200;
    $finish();
  end

  initial
    begin
      $dumpfile("dff_tb.vcd");
    end

endmodule

Can anyone whats wrong? I used Cadence Xcelium

2

In reply to kevin488:

Your call to uvm_config_db set() is incorrect. Your first argument (“null” in quotes) is a packed array. The expected argument is of type uvm_component.

You want:


uvm_config_db#(virtual d_ff_intf)::set(null,"test","d_ff_intf",vif);