Enabling logging macros in RTL

UVM
,
1

Has anybody enabled usage of the UVM logging macros in RTL (which is SystemVerilog) ? If so, could you please share how you got this done ?

2

In reply to DVJoe:

Most synthesis tools already ignore $display messages, but I don’t suppose they have gotten around to ignoring UVM messages.

All you need to do is put this code at the beginning of any RTL module that wants to use the UVM messages

`ifdef SYNTHESIS
`define uvm_info(ID,MSG,VERBOSITY) $display({"Info: ",ID,":",MSG});
`define uvm_warning(ID,MSG) $display({"Warning: ",ID,":",MSG});
`define uvm_error(ID,MSG) $display({"Error: ",ID,":",MSG});
`define uvm_fatal(ID,MSG) $display({"Fatal: ",ID,":",MSG});
`else
`include "uvm_macros.svh"
import uvm_pkg::*;
`endif

Now you can use the UVM reporting macros in your RTL code.