In reply to samerh:
UVM elaboration refers to the dynamic construction of your class-based testbench architecture at simulation time 0. It is broken up into a series of two steps: the build_phase and the connect_phase. There is no actual named elaboration_phase, but there is an end_of_elaboration_phase that follows the connect_phase. By the time you get to end_of_elaboration, all uvm_components are constructed and the connection made between them.