How to Know Input and output Speed of the DUT??
In reply to Subbi Reddy:
The easiest way is to do a waveform inspection to verify your clock frequencies.
Please show me with one example.
In reply to Subbi Reddy:
You can simply write an assertion/checker for i/p clk freq and o/p clk freq just by considering on_time and off_time.
Thanks,
Kishore
In reply to Subbi Reddy:
Consider I have DUT feeding clock is 200MHZ clock and outside is 200MHZ, How to makesure 200MHZ is getting outside or not??
Simulating RTL the clock frequency does not matter. You can run any speed.
Your design will gnereate your output signals with the output clock speed. You have to makke sure this clock speed is correct.
You can observe the input as well as the output clock speed by using SV assertions.
Please provide one example code with assertion
In reply to Subbi Reddy:
You can use the code below to calculate frquency of the signal
``` verilog
realtime current,prev=0;
always @ (posedge signal) begin
current = $realtime;
$display("Freq of the signal is : %4.2f",1.0/(current - prev));
prev = current;
end
In reply to Subbi Reddy:
How to Know Input and output Speed of the DUT??
write an assertion for the generated clock using the realtime of the clock and compare them to a constant parameter with fixed or given clock time period.
maybe this assertion may help your problem
In reply to Subrahmanyam:
please provide with full assertion code for comparing output and input data of the DUT with 2 clock cycle
In reply to Subbi Reddy:
Try using this assertion for checking the clock freq
assert property check_freq(2.85); //freq in ns
property check_frq(real expected_freq);
time curr_time;
@(posedge clk) (`1, curr_time=$time) ##1 ($time - curr_time)) == expected_freq;
endproperty