Hi
I wonder how much DUT signal visibility we can get when using hardware accelerated simulation. If I understand correctly, we do not get full visibility, as in the case of pure simulation. We can view only the recorded transaction fields which are recorded using the `uvm_record_field macro, is that correct? If this is the case, then emulation, although a great tool for accelerating verification, does not completely expel the need to do pure software simulations, specially when, through emulation, we find some problem with the design. In such a case we may have to perform a simulation in order to trace the root of the problem. Is that right?
I would be grateful if you help me correct any misunderstandings in what I wrote above.
Thanks in advance.
Farhad
In reply to Farhad:
It depends on what emulation platform you are using. Some provide entire design visibility with no additional options required by the user, while some require you to specify in advance what you desire to observe. You will need to discuss the features with your vendor of choice.