DUT requirements to change only one signal at a time

I have a DUT which has 5 signals which i am driving from my testbench. The problem is i am driving all the signals at the same time on the interface. The requirement from the FSM is to change only one signal at a time. I have a seq_item with 5 signals. How do i control/drive one at a time? If this is not efficient way, what are alternative options we have?

In reply to rag123:

You are mixing the terms “drive” and “change”. Can you be more specific?

Do you mean something like this: Change in bits between requests constraint | Verification Academy

In reply to rag123:

Hi,

As per my understanding of your requirement, you may need to mimic the FSM state change conditions in your driver run_phase task, and based on the state you may drive the appropriate signal. You might also need to declare some internal flags specific to your requirements to control/time the state change.

Thanks.