DUT output coming as XX (unknown values)

Hi All,
Here is the small example to drive some values from driver and display the same in DUT. But output is coming as XX, may I know where I went wrong?

//DUT CODE
module dut(dut_if dif);
import uvm_pkg::*;
always @(posedge dif.clock)
begin
    `uvm_info("", $sformatf("DUT Received cmd=%h H, data=%h H, addr=%h H",
              dif.cmd, dif.data, dif.address ), UVM_MEDIUM )  
end
endmodule

//INTERFACE CODE
interface dut_if;

logic clock, reset;
logic cmd;
logic [7:0] data;
logic [7:0] address;

endinterface
//ENVIRONMENT
class my_env extends uvm_env;
`uvm_component_utils(my_env)

function new(string name, uvm_component parent);
super.new(name, parent);
endfunction: new

function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction: build_phase

endclass: my_env 

//TEST 
class my_test extends uvm_test;
`uvm_component_utils(my_test)

my_env my_env_h;

function new(string name, uvm_component parent);
super.new(name, parent);
endfunction: new

function void build_phase(uvm_phase phase);
super.build_phase(phase);;
my_env_h = my_env::type_id::create("my_env_h", this);
endfunction: build_phase 

task run_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info("TOP TEST", "HELLO_BEGINS", UVM_MEDIUM);
#80;
`uvm_info("TOP TEST", "HELLO_ENDS", UVM_MEDIUM);
phase.drop_objection(this);
endtask

endclass: my_test

//TOP CODE
module top;

import uvm_pkg::*;
import my_pkg::*;

dut_if dut_if1 ();
dut dut1 (.dif(dut_if1) );

initial begin
dut_if1.clock = 0;
forever #5 dut_if1.clock = ~dut_if1.clock;
end

initial begin
uvm_config_db #(virtual dut_if)::set( null, "*", "dut_if", dut_if1 );
uvm_top.finish_on_completion = 1;
run_test("my_test");
end

endmodule

//DRIVER
class my_driver extends uvm_driver;
`uvm_component_utils(my_driver)

virtual dut_if dut_vi;

function new(string name, uvm_component parent);
super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

if (! uvm_config_db #(virtual dut_if)::get (this, "", "dut_if", dut_vi) )
    `uvm_error("", "uvm_config_db get failed") 

endfunction

task run_phase(uvm_phase phase);
  forever
    begin
@(posedge dut_vi.clock);

dut_vi.cmd      <= $urandom; 
dut_vi.data     <= $urandom;
dut_vi.address  <= $urandom;

end
endtask
endclass

//////////////////////////////////////////////////////////////////
output
UVM_INFO my_test.svh(19) @ 0: uvm_test_top [TOP TEST] HELLO_BEGINS
UVM_INFO dut.sv(10) @ 5: reporter DUT Received cmd=x H, data=xx H, addr=xx H
UVM_INFO dut.sv(10) @ 15: reporter DUT Received cmd=x H, data=xx H, addr=xx H

These are the possible methods tried, but I got the same results.

  1. Replaced <= operator with = operator in driver. Like;
    dut_vi.cmd = $urandom;

  2. Replacing $sformatf in DUT with $psprintf.

  3. Changing data type in interface from logic to bit.

In reply to Mahesh K:

There is no instance of your Driver in the env!

In reply to chr_sue:

Hi,

Lets assume, I will create a instance of driver in environment like;

my_driver obj_driver;

Then do I need to use again “uvm_config_db… get()” in environment?

you have to create a object of a driver in the environment/test for the Driver, and
my_driver obj_driver; and then the create menthod for the same to create the handle and actual memory space of the object.
doing uvmuvm_config_db… get() , please see you are getting the Virtual interface , and you generally use that in the driver , why again you want to get it in the env, no need!!!

just add the driver object and create the obeject

In reply to Mahesh K:

my_driver obj_driver;
does not create an object. It defines only a reference.
You have to call the type_id::create method of the factory.
This creates your object. In this object you have to call the get method of uvm_config_db to get the virtual Interface.

Hi Thank you all, got expected output.

Please forgive me for late response.

Here is the output;
UVM_INFO my_test.svh(19) @ 0: uvm_test_top [TOP TEST] HELLO_BEGINS
UVM_INFO dut.sv(10) @ 5: reporter DUT Received cmd=x H, data=xx H, addr=xx H
UVM_INFO dut.sv(10) @ 15: reporter DUT Received cmd=0 H, data=da H, addr=c3 H
UVM_INFO dut.sv(10) @ 25: reporter DUT Received cmd=1 H, data=c4 H, addr=44 H
UVM_INFO dut.sv(10) @ 35: reporter DUT Received cmd=1 H, data=be H, addr=25 H
UVM_INFO dut.sv(10) @ 45: reporter DUT Received cmd=0 H, data=b7 H, addr=73 H
UVM_INFO dut.sv(10) @ 55: reporter DUT Received cmd=0 H, data=64 H, addr=4b H
UVM_INFO dut.sv(10) @ 65: reporter DUT Received cmd=1 H, data=08 H, addr=85 H
UVM_INFO dut.sv(10) @ 75: reporter DUT Received cmd=1 H, data=ae H, addr=e5 H
UVM_INFO my_test.svh(21) @ 80: uvm_test_top [TOP TEST] HELLO_ENDS