Hi
My question is related to this page of the Cookbook.
As the benefits of the dual top architecture, it is written in the above link that:
“Specifically, it can facilitate the use of multi-processor platforms for simulation, the use of compile and run-time optimization techniques…”
I need some help understanding the above.
My first question is, if I understand correctly, the use of multi-processor platforms for simulation is beneficial by assigning the hdl domain to one processor, and the hvl domain do another processor, is that correct?
My second question is related to the “use of compile and run-time optimization techniques”. Could you please explain more about this, what specific techniques are meant here?
Thank you very much
In reply to Farhad:
Answering your first question, yes the intent is to split the simulation up into different processors; more specifically one software engine and one hardware engine like an emulator or FPGA prototype.
You second question borders on tool specific behavior. The general idea is sometimes you have many tests to run on a single DUT and do not want to incur the overhead of compiling and optimizing the DUT every time.