I GOT THIS ERROR
** Error: (vsim-3978) top.sv(81): Cannot assign a packed type to an unpacked type.
Time: 0 ns Iteration: 0 Instance: /top File: top.sv
** Error: (vsim-3978) top.sv(82): Cannot assign a packed type to an unpacked type.
Time: 0 ns Iteration: 0 Instance: /top File: top.sv
** Error: (vsim-3978) top.sv(83): Cannot assign a packed type to an unpacked type.
Time: 0 ns Iteration: 0 Instance: /top File: top.sv
** Error: (vsim-3978) top.sv(84): Cannot assign a packed type to an unpacked type.
Time: 0 ns Iteration: 0 Instance: /top File: top.sv
** Warning: (vsim-3015) top.sv(74): [PCDPC] - Port size (64 or 64) does not match connection size (1) for port ‘data_in’. The port definition is at: E:/EDiFY LAB ASSIGNMENT/naresh_ram/ram_soc.v(26).
Region: /top/DUV
** Warning: (vsim-3015) top.sv(74): [PCDPC] - Port size (10 or 10) does not match connection size (1) for port ‘rd_address’. The port definition is at: E:/EDiFY LAB ASSIGNMENT/naresh_ram/ram_soc.v(27).
Region: /top/DUV
** Warning: (vsim-3015) top.sv(74): [PCDPC] - Port size (10 or 10) does not match connection size (1) for port ‘wr_address’. The port definition is at: E:/EDiFY LAB ASSIGNMENT/naresh_ram/ram_soc.v(28).
Region: /top/DUV
** Warning: (vsim-3015) top.sv(74): [PCDPC] - Port size (64 or 64) does not match connection size (1) for port ‘data_out’. The port definition is at: E:/EDiFY LAB ASSIGNMENT/naresh_ram/ram_soc.v(31).
Region: /top/DUV
TOP
module top;
// import ram_test_pkg
// import ram_test _pkg::*;
//import uvm_pkg.sv
import uvm_pkg::*;
// Generate clock signal
bit clock;
always
#10 clock=!clock;
// Instantiate 4 ram_if interface instances in0,in1,in2,in3 with clock as input
//ram_if in0;
ram_if DUV_IF(in0);
ram_if DUV_IF0(in1);
ram_if DUV_IF1(in2);
ram_if DUV_IF2(in3);
// Instantiate 4 ram_soc duv instances mif0,mif1,mif2,mif3 with interface as input
ram_soc DUV(.data_in(in0),
.rd_address(in1),
.wr_address(in2),
.data_out(in3));
// In initial block
initial begin
//set the virtual interface instances as strings vif_0,vif_1,vif_2,vif_3 using the uvm_config_db
uvm_config_db #(virtual ram_if)::set(null,"*","vif_0",in0);
uvm_config_db #(virtual ram_if)::set(null,"*","vif_1",in1);
uvm_config_db #(virtual ram_if)::set(null,"*","vif_2",in2);
uvm_config_db #(virtual ram_if)::set(null,"*","vif_3",in3);
// Call run_test
run_test("ram_base_test");
end
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
DUT
`define RAM_WIDTH 64
`define ADDR_SIZE 12
module ram_soc ( clk,
data_in,
rd_address,
wr_address,
read,
write,
data_out) ;
input clk; // RAM Clock
input [`RAM_WIDTH-1 : 0] data_in; // Data Input
input [`ADDR_SIZE-1 : 0] rd_address; // Read Address
input [`ADDR_SIZE-1 : 0] wr_address; // Write Address
input read; // Read Control
input write; // Write Control
output tri [`RAM_WIDTH-1 : 0] data_out; // Data Output
Any help would be greatly appreciated, thanks!