Driving Internal Signals in DUT

UVM
1

I have to drive internal signals of dut from the uvm driver.without using “force”, I read in some article that bind can be used. I did bind in my top module. Tried making that instance as virtual using uvm_configdb::set.But I am not able to do that. is it because of any syntax error?Please help

seral_write in0(clk);//interface instance
bind cpu_write : DUT serial_write b0(DUT.en);//bind

initial
begin

//set the virtual interface using the uvm_config_db

uvm_config_db #(virtual serial_write)::set(null,"*","vif",in0);  // setting interface instance
uvm_config_db #(virtual serial_write)::set(null,"*","vifInt",in0.b0);    //how to set bind interface
run_test();

end

endmodule

Thanks in advance ,
Roopa

2

In reply to roopatoms:
What kind of syntax error do you get? Please give the details.

3

In reply to chr_sue:

i am getting like hierarchial path is not correct"in0.b0"

Please suggest me how to drive internal signal of dut using bind.(syntax)

and how to pass it to uvm_config_db

4

In reply to roopatoms:

Why can’t you use a force statement? Depending on your design, using a bind may or may not work. If the signal that you are connecting to has other drivers, bind will only act as another driver which may result in ‘X’ values. Using a force will ensure that only the signal from your interface will be driven to the DUT signal.

5

In reply to roopatoms:

Your problem is the hierarchical path in the uvm_config_db.
Is it correct the internal signal you want to set is part of your SV interface instancee in0?
If so you do not need an additional interface instance.
With the bind construct you have 2 options:
(1) binding to a design in your DUT
(2) binding to a certain instance in your DUT.

In case (1) you do not need to define an hierarchical path. In case (2) you have to specify the hierarchical path to the instance.

6

In reply to roopatoms:

Regardless of whether what you’re trying to do is the best way of meeting your requirements (I think maybe :-)), from an SV/UVM perspective, you should probably be able to get it running.

See it working on edaplayground here

7

In reply to cgales:

I tried force statement. It was working. But, please tell me how to use bind for connecting the internal signals of dut which is of wire type, like

“bind Dut: DutInst serial_write b0(DutInst.en)”;//dut is my module.‘en’ is the internal signal

while trying to set bo in uvm_config_db, I am getting undefined varibale b0.

8

In reply to roopatoms:

Could you please show the bind command you are using. Of course you have to define the corresponding signal as net (wire) and not as a variable.

9

In reply to chr_sue:

This is my top module:

module top;
import uvm_pkg::;
import pkg::;
//clk

bit clk;
always #10 clk=~clk;

// instantiating

serial_write in0(clk); // interface instance
cpu_write DUT(.clk(clk),.reset(in0.reset), .enable(in0.enable), .sin(in0.sin),.addr(in0.addr),.data(in0.data),.count(in0.count));

bind cpu_write: DUT serial_write b0(DUT.en); //bind

initial
begin

//set the virtual interface using the uvm_config_db

uvm_config_db #(virtual serial_write)::set(null,"*","vif",in0);// how to give bind instance
run_test();

end

endmodule

10

In reply to roopatoms:

It looks like your bind construct is not correct. Ther syntax is like this:

bind <module to bind to> <module/interface doing the operation> <inst name of this module> (variables/nets under consideration);
11

In reply to chr_sue:

So, in my scenario,it will be
serial_write in0(clk); // interface instance
cpu_write DUT(.clk(clk),.reset(in0.reset), .enable(in0.enable), .sin(in0.sin),.addr(in0.addr),.data(in0.data),.count(in0.count));
" bind cpu_write cpu_if b0(en)";

I checked it also,but getting same error:undefined variable b0

12

In reply to roopatoms:

Your posts make it seem that you have some misunderstandings about what bind is used for.

It looks like you have an interface ‘serial_write’, which you instantiate at the top level of your testbench as ‘in0’.

Your DUT ‘cpu_write’ is instantiated in your testbench as ‘DUT’ and the ports are connected to the internal signals of the interface ‘in0’.

It then looks like you are trying to bind another instance of ‘serial_write’ inside the DUT? Is this correct? If you already have an instance of ‘serial_write’ at the top level, why do you want another instance inside of the DUT?

Perhaps if you can clearly describe what you want to accomplish along with posting a complete example that can be compiled and run, we can provide further assistance.