Hi,
I’m trying to force internal DUT signals by a SV module. But signals are not driven.
module dut_bind#(string agent_name = "",
string if_instance_name = "vif")
(input logic clk,
input logic reset_n,
input logic valid,
input logic [7:0] data
);
import uvm_pkg::*;
vif vif_i (.clk(clk), .reset_n(reset_n));
initial begin
uvm_config_db#(virtual vif )::set(null, $sformatf("uvm_test_top.tb.%s", agent_name), if_instance_name, vif_i);
force valid = vif_i.valid;
force data = vif_i.data;
end
endmodule
bind
`DUT_PATH.WRAPPER_I
dut_bind#(.agent_name("core_agent"),
.if_instance_name("vif")
)
dut_bind_i
(
.clk (ck_xgmii_x_a),
.reset_n(HRESETn),
.valid (internal_valid),
.data (internal_data));
Is there any way to drive DUT signals using module ports?