I am trying implement virtual sequencer by having multiple sequences within a single sequence. I only have one sequencer but still need to reuse the sequences for a complex scenario. I am seeing xxx values at the driver while transaction values are proper at the sequencer. I feel the I have made the proper connections. Following is my code :
program dut_test();
import uvm_pkg::*;
import dut_pkg_uvm::*;
`include "uvm_macros.svh"
class dut_level0_preset_lock extends dut_test_base;
`uvm_component_utils(dut_level0_preset_lock)
dut_preset_lock_seq dut_preset_seq;
function new (string name = "dut_level0_preset_lock", uvm_component parent=null);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
// End of Elaboration Phase
function void end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
dut_preset_seq = dut_preset_lock_seq::type_id::create("dut_preset_seq");
dut_preset_seq.m_sequencer = m_env.m_agent.m_sequencer;
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this, "Starting UVM Preset lock test");
`uvm_info("TEST", "START OF TEST", UVM_LOW)
`uvm_info("TEST", "START OF PRESET SEQUENCE", UVM_LOW)
dut_preset_seq.start(null);//m_env.m_agent.m_sequencer);
`uvm_info("TEST", "PASS", UVM_LOW)
phase.drop_objection(this, "UVM Preset lock test finished");
endtask : run_phase
endclass : dut_level0_preset_lock
initial begin
run_test("dut_level0_preset_lock");
end
endprogram
class Seq_hard_reset extends uvm_sequence #(dut_txn);
function new(string name="");
super.new(name);
endfunction
`uvm_object_utils(Seq_hard_reset)
virtual task body;
dut_txn req = dut_txn::type_id::create("req");
`uvm_info(get_type_name(),"Starting reset request", UVM_MEDIUM);
start_item(req);
req.reset <= 1'b1;
finish_item(req);
`uvm_info(get_type_name(),"Done with hard reset request", UVM_MEDIUM);
endtask : body
endclass
class Seq_enable_clk_gen extends uvm_sequence #(dut_txn);
`uvm_object_utils(Seq_enable_clk_gen)
function new(string name="Seq_enable_clk_gen");
super.new(name);
endfunction
dut_txn req;
virtual task body;
req = dut_txn::type_id::create("req");
`uvm_info(get_type_name(),"Starting clk generation request", UVM_MEDIUM);
start_item(req);
req.reset <= 1'b0;
req.clk_gen <= 1'b1;
finish_item(req);
`uvm_info(get_type_name(),"Done with clk genereation request", UVM_MEDIUM);
`uvm_info("seq_body_clk_en", req.convert2string(), UVM_LOW);
endtask : body
endclass
class preset_lock_base_seq extends uvm_sequence #(dut_txn);
//PSET Mode
rand bit [4:0] pset_mode;
dut_txn req;
function new(string name="preset_lock_base_seq");
super.new(name);
endfunction
`uvm_object_utils(preset_lock_base_seq)
virtual task body;
`uvm_info(get_type_name(),"Starting preset_base request", UVM_MEDIUM);
req = dut_txn::type_id::create("req");
start_item(req);
req.reset <= 1'b0;
req.valid <= 1'b1;
pset_mode <= 5'd2;
req.udb <= {1'b0,pset_mode};
req.enable <= 1'b1;
req.parasel <= 1'b1;
req.delay <= 15;
finish_item(req);
`uvm_info(get_type_name(),"Done with preset base request", UVM_MEDIUM);
`uvm_info("seq_body_preset_base", req.convert2string(), UVM_LOW);
endtask : body
endclass
class dut_preset_lock_seq extends uvm_sequence #(dut_txn);
`uvm_object_utils(dut_preset_lock_seq)
Seq_hard_reset reset_seq;
Seq_enable_clk_gen en_clk_gen_seq;
preset_lock_base_seq preset_base_seq;
dut_sequencer m_sequencer;
function new(string name = "dut_preset_lock_seq");
super.new(name);
endfunction
task body;
reset_seq = Seq_hard_reset::type_id::create("reset_seq");
en_clk_gen_seq = Seq_enable_clk_gen :: type_id::create("en_clk_gen_seq");
preset_base_seq = preset_lock_base_seq :: type_id::create("preset_base_seq");
begin
//reset the dut
reset_seq.start(m_sequencer,this);
#2ns;
//enable_clk_gen
en_clk_gen_seq.start(m_sequencer,this);
#2ns;
preset_base_seq.start(m_sequencer,this);
#6ns;
end
endtask: body
endclass:dut_preset_lock_seq