I've had some problems to verify one block. This block do some operations of transmit (modulate) and receive (demodulate) signals. The block contains a register bank that have the command register, the status register, and the received data register. My model (preditor) do some calculations with the received data and stores the message at the correct register. The problem that i have had is that my model is behavioral and their calculations is instantaneous, but my DUT have a delay and put some status on the status register (E.G. RECEIVING). If there is a requisition of read the status register will be an incorrect comparation between the model and the DUT, but it isn't necessary a bug.
There is a correct method do handle situation like this?